component
A6213KLJTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC LED Drivers, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA6213KLJTR-T
Allegro MicroSystems, LLC · LED Drivers · SOIC-8-EP
A6213KLJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply voltage input, specified from 6 V to 48 V with absolute maximum rating of -0.3 V to 50 V. |
| 2 | TON | passive | Regulator on-time setting resistor terminal; the resistor connects between VIN and TON and sets the switching frequency, with an internal resistance of 5 kΩ. |
| 3 | EN | input | Logic input for enable and PWM dimming, with logic high at 1.8 V minimum and logic low at 0.4 V maximum; it is high-voltage tolerant but a 1 kΩ series resistor is required if it is driven above the VIN voltage. |
| 4 | CS | input | Drive output current sense feedback, with absolute maximum voltage of -0.3 V to 7 V and average regulation threshold VCSREG of 200 mV typical (187.5 mV to 210 mV). |
| 5 | VCC | power_out | Internal linear regulator output, regulated at 5.1 V to 5.7 V with absolute maximum of 7 V to GND, and not designed to drive an external load. |
| 6 | GND | power_in | Ground terminal for the device. |
| 7 | BOOT | passive | DMOS gate driver bootstrap terminal, with bootstrap drive voltage rated from -0.3 V to VIN + 8 V. |
| 8 | SW | output | Switched output terminal, rated from -1.5 V to VIN + 0.3 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8-EP |
| Category | Nixie Tube Driver/LED Driver |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | -0.3 | 50 | V | 2 | ||
| Bootstrap Drive Voltage | VBOOT | -0.3 | V | max printed as VIN +8 V | 2 | ||
| Switching Voltage | VSW | -1.5 | V | max printed as VIN +0.3 V | 2 | ||
| Linear Regulator Terminal | VCC | -0.3 | 7 | V | VCC to GND | 2 | |
| Enable and TON Voltage | VEN, VTON | -0.3 | V | max printed as VIN +0.3 V | 2 | ||
| Current Sense Voltage | VCS | -0.3 | 7 | V | 2 | ||
| Maximum Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 2 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 35 | °C/W | On 4-layer PCB based on JEDEC standard | 2 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 62 | °C/W | On 2-layer generic test PCB with 0.8 in.2 of copper area each side | 2 | ||
| Package Thermal Resistance (Junction to Pad) | RθJP | 2 | °C/W | 2 | |||
| Input Supply Voltage | VIN | 6 | 48 | V | 4 | ||
| VIN Pin Shutdown Current | IINSD | 1 | 10 | µA | EN shorted to GND | 4 | |
| Buck Switch Current Limit Threshold | ISWLIM | 3 | 4 | 5 | A | A6213 | 4 |
| Buck Switch On-Resistance | RDS(on) | 0.25 | 0.4 | Ω | VBOOT = VIN + 4.3 V, TA = 25°C, ISW = 1 A | 4 | |
| BOOT Undervoltage Lockout Threshold | VBOOTUV | 1.7 | 2.9 | 4.3 | V | VBOOT to VSW increasing | 4 |
| Switching Minimum Off-Time | tOFFmin | 110 | 150 | ns | VCS = 0 V | 4 | |
| Switching Minimum On-Time | tONmin | 110 | 150 | ns | 4 | ||
| Selected On-Time | tON | 800 | 1000 | 1200 | ns | VIN = 24 V, VOUT = 12 V, RON = 137 kΩ | 4 |
| Load Current Sense Regulation Threshold | VCSREG | 187.5 | 200 | 210 | mV | VCS decreasing, SW turns on | 4 |
| VCC Regulated Output | VCC | 5.1 | 5.4 | 5.7 | V | 0 mA < ICC < 5 mA, VIN > 6 V | 4 |
| VCC Current Limit | ICCLIM | 5 | 20 | mA | VIN = 24 V, VCC = 0 V | 4 | |
| Logic High Voltage | VIH | 1.8 | V | VEN increasing | 4 | ||
| Logic Low Voltage | VIL | 0.4 | V | VEN decreasing | 4 | ||
| Maximum PWM Dimming Off-Time | tPWML | 10 | 17 | ms | Measured while EN = low, during dimming control, and internal references are powered-on (exceeding tPWML results in shutdown) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | It is lead (Pb) free, with 100% matte-tin leadframe plating. A62131-DS, Rev. 10 | 1 |
CAD (KiCad official)
- Symbol:
A6213KLJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
a6213kljtr-t-etched.step/a6213kljtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a6213kljtr-t.step/a6213kljtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (18 pp, sha256
20eecae2a2983b2f, retrieved 2026-11-02, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).