component

CD74HC175E

Public Made by Adom

by adom

Texas Instruments Flip Flops, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icscd74hc175efactory-2.0.0extractor-text

Verified CD74HC175E

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC175E · PDIP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 16-page datasheet
  • ✓distributor: lcsc C1549840, digikey 296-33038-5-ND, mouser 595-CD74HC175E
  • ✓family: DIP-16_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-logpnp7p/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc175e.kicad_sym✓ cd74hc175e.kicad_mod✓ cd74hc175e.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CD74HC175E

Texas Instruments · Flip Flops · PDIP-16

CD74HC175E from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low asynchronous master reset; a low level resets all four Q outputs to logic 0 and all Q outputs to logic 1, independent of the clock.
2 Q0 output True output of flip-flop 0, which follows D0 on the positive clock edge and is reset to logic 0 by MR low.
3 ~Q0 output Complementary output of flip-flop 0, which is the inverse of Q0 and is reset to logic 1 by MR low.
4 D0 input Data input to flip-flop 0, transferred to the outputs on the positive-going edge of CP.
5 D1 input Data input to flip-flop 1, transferred to the outputs on the positive-going edge of CP; HCT inputs accept LSTTL levels with VIL max 0.8 V and VIH min 2 V.
6 ~Q1 output Complementary output of flip-flop 1, which is the inverse of Q1 and is reset to logic 1 by MR low.
7 Q1 output True output of flip-flop 1, which follows D1 on the positive clock edge and is reset to logic 0 by MR low.
8 GND power_in Ground reference for the device.
9 CP input Common clock input; data on Dn is transferred to Qn and ~Qn on the positive-going edge of the clock pulse.
10 Q2 output True output of flip-flop 2, which follows D2 on the positive clock edge and is reset to logic 0 by MR low.
11 ~Q2 output Complementary output of flip-flop 2, which is the inverse of Q2 and is reset to logic 1 by MR low.
12 D2 input Data input to flip-flop 2, transferred to the outputs on the positive-going edge of CP.
13 D3 input Data input to flip-flop 3, transferred to the outputs on the positive-going edge of CP.
14 ~Q3 output Complementary output of flip-flop 3, which is the inverse of Q3 and is reset to logic 1 by MR low.
15 Q3 output True output of flip-flop 3, which follows D3 on the positive clock edge and is reset to logic 0 by MR low.
16 VCC power_in Supply voltage: 2 V to 6 V for HC types and 4.5 V to 5.5 V for HCT types (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Level Input Voltage VIH 1.5 V HC types, VCC=2V, -55°C to 125°C 3
High Level Input Voltage VIH 3.15 V HC types, VCC=4.5V, -55°C to 125°C 3
High Level Input Voltage VIH 4.2 V HC types, VCC=6V, -55°C to 125°C 3
Low Level Input Voltage VIL 0.5 V HC types, VCC=2V, -55°C to 125°C 3
Low Level Input Voltage VIL 1.35 V HC types, VCC=4.5V, -55°C to 125°C 3
Low Level Input Voltage VIL 1.8 V HC types, VCC=6V, -55°C to 125°C 3
High Level Output Voltage CMOS Loads VOH 1.9 V VI=VIH or VIL; IO=-0.02mA; VCC=2V; -55°C to 125°C 3
High Level Output Voltage CMOS Loads VOH 4.4 V VI=VIH or VIL; IO=-0.02mA; VCC=4.5V; -55°C to 125°C 3
High Level Output Voltage CMOS Loads VOH 5.9 V VI=VIH or VIL; IO=-0.02mA; VCC=6V; -55°C to 125°C 3
High Level Output Voltage TTL Loads VOH 3.7 V IO=-4mA; VCC=4.5V; -55°C to 125°C 3
High Level Output Voltage TTL Loads VOH 5.2 V IO=-5.2mA; VCC=6V; -55°C to 125°C 3
Low Level Output Voltage CMOS Loads VOL 0.1 V VI=VIH or VIL; IO=0.02mA; VCC=2V; -55°C to 125°C 3
Low Level Output Voltage TTL Loads VOL 0.4 V IO=4mA; VCC=4.5V; -55°C to 125°C 3
Input Leakage Current II -1 1 µA VI=VCC or GND; VCC=6V; -55°C to 125°C 3
Quiescent Device Current ICC 160 µA VI=VCC or GND; IO=0; VCC=6V; -55°C to 125°C 3
Supply Voltage Range, VCC (HC types) VCC 2 6 V HC types 3
Temperature Range TA -55 125 °C 3
Input Rise and Fall Time 1000 ns VCC=2V 3
Input Rise and Fall Time 500 ns VCC=4.5V 3
Input Rise and Fall Time 400 ns VCC=6V 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Diode Current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 3
DC Output Diode Current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 3
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V 3
DC VCC or Ground Current ICC or IGND -50 50 mA 3
Maximum Junction Temperature 150 °C 3
Maximum Storage Temperature Range -65 150 °C 3
Maximum Lead Temperature (Soldering) 300 °C Soldering 10s (SOIC lead tips only) 3
Clock Pulse Width tw 120 ns HC types, VCC=2V, -55°C to 125°C 4
Clock Pulse Width tw 24 ns HC types, VCC=4.5V, -55°C to 125°C 4
Clock Pulse Width tw 20 ns HC types, VCC=6V, -55°C to 125°C 4
MR Pulse Width tw 120 ns HC types, VCC=2V, -55°C to 125°C 4
MR Pulse Width tw 24 ns HC types, VCC=4.5V, -55°C to 125°C 4
MR Pulse Width tw 20 ns HC types, VCC=6V, -55°C to 125°C 4
Setup Time, Data to Clock tSU 120 ns HC types, VCC=2V, -55°C to 125°C 5
Setup Time, Data to Clock tSU 24 ns HC types, VCC=4.5V, -55°C to 125°C 5
Setup Time, Data to Clock tSU 20 ns HC types, VCC=6V, -55°C to 125°C 5
Hold Time, Data to Clock tH 5 ns HC types, VCC=2V, -55°C to 125°C 5
Removal Time, MR to Clock tREM 5 ns HC types, VCC=2V, -55°C to 125°C 5
Clock Frequency fMAX 4 MHz HC types, VCC=2V, -55°C to 125°C 5
Clock Frequency fMAX 20 MHz HC types, VCC=4.5V, -55°C to 125°C 5
Clock Frequency fMAX 23 MHz HC types, VCC=6V, -55°C to 125°C 5
Propagation Delay, Clock to Q or Q̄ tPLH, tPHL 265 ns CL=50pF; Input tr, tf=6ns; VCC=2V; -55°C to 125°C 5
Propagation Delay, Clock to Q or Q̄ tPLH, tPHL 53 ns CL=50pF; Input tr, tf=6ns; VCC=4.5V; -55°C to 125°C 5
Propagation Delay, Clock to Q or Q̄ tPLH, tPHL 45 ns CL=50pF; Input tr, tf=6ns; VCC=6V; -55°C to 125°C 5
Propagation Delay, MR to Q or Q̄ tPLH, tPHL 265 ns CL=50pF; Input tr, tf=6ns; VCC=2V; -55°C to 125°C 5
Propagation Delay, MR to Q or Q̄ tPLH, tPHL 53 ns CL=50pF; Input tr, tf=6ns; VCC=4.5V; -55°C to 125°C 5
Propagation Delay, MR to Q or Q̄ tPLH, tPHL 45 ns CL=50pF; Input tr, tf=6ns; VCC=6V; -55°C to 125°C 5
Output Transition Times tTLH, tTHL 110 ns CL=50pF; Input tr, tf=6ns; VCC=2V; -55°C to 125°C 5
Output Transition Times tTLH, tTHL 22 ns CL=50pF; Input tr, tf=6ns; VCC=4.5V; -55°C to 125°C 5
Output Transition Times tTLH, tTHL 19 ns CL=50pF; Input tr, tf=6ns; VCC=6V; -55°C to 125°C 5
Input Capacitance CIN 10 pF -55°C to 125°C 5
Thermal Resistance, Junction to Ambient (E PDIP package) θJA 67 °C/W E (PDIP) package, typical, per JESD 51-7 3

CAD (KiCad official)

  • Symbol: CD74HC175E
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc175e-etched.step / cd74hc175e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc175e.step / cd74hc175e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 3348189f53a06a61, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF