component
PDTB113ZUX
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-323-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPDTB113ZUX
Nexperia · Digital Transistors · SOT-323-3
PDTB113ZUX from Nexperia, in a SOT-323-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | input (base) | input | Input (base) of the built-in transistor, driving the internal bias resistor R1; for PDTB113ZU the input voltage VI is specified from -10 V to +5 V (VEBO limit 5 V). |
| 2 | GND (emitter) | power_in | Emitter, labelled GND in the datasheet, which is the common ground reference; for PDTB113ZU the emitter-base voltage VEBO is limited to 5 V. |
| 3 | output (collector) | output | Output (collector) of the built-in transistor, rated for a collector-emitter voltage VCEO of 50 V maximum and an output current IO of 500 mA maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-323-3 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-emitter voltage | VCEO | 50 | V | open base | 3 | ||
| Collector-base voltage | VCBO | 50 | V | open emitter | 3 | ||
| Emitter-base voltage (PDTB113ZU) | VEBO | 5 | V | open collector | 3 | ||
| Input voltage (PDTB113ZU) | VI | -10 | 5 | V | 3 | ||
| Output current | IO | 500 | mA | 3 | |||
| Total power dissipation | Ptot | 300 | mW | Tamb 25 C; FR4 PCB, single-sided copper, standard footprint [1] | 4 | ||
| Total power dissipation | Ptot | 425 | mW | Tamb 25 C; FR4 PCB, 4-layer copper, standard footprint [2] | 4 | ||
| Junction temperature | Tj | 175 | C | 4 | |||
| Ambient temperature | Tamb | -55 | 175 | C | 4 | ||
| Storage temperature | Tstg | -55 | 175 | C | 4 | ||
| Thermal resistance from junction to ambient | Rth(j-a) | 500 | K/W | in free air; FR4 PCB, single-sided copper [1] | 4 | ||
| Thermal resistance from junction to ambient | Rth(j-a) | 353 | K/W | in free air; FR4 PCB, 4-layer copper [2] | 4 | ||
| Collector-base cut-off current | ICBO | 100 | nA | VCB = 40 V; IE = 0 A | 6 | ||
| Collector-emitter cut-off current | ICEO | 0.5 | A | VCE = 50 V; IB = 0 A | 6 | ||
| Emitter-base cut-off current (PDTB113ZU) | IEBO | 0.8 | mA | VEB = 5 V; IC = 0 A | 6 | ||
| DC current gain (PDTB113ZU) | hFE | 70 | VCE = 5 V; IC = 50 mA | 6 | |||
| Collector-emitter saturation voltage | VCEsat | 100 | mV | IC = 50 mA; IB = 2.5 mA | 6 | ||
| Off-state input voltage (PDTB113ZU) | VI(off) | 0.3 | 0.6 | 1 | V | VCE = 5 V; IC = 100 A | 6 |
| On-state input voltage (PDTB113ZU) | VI(on) | 0.4 | 0.8 | 1.4 | V | VCE = 0.3 V; IC = 20 mA | 6 |
| Bias resistor 1 (input) (PDTB113ZU) | R1 | 0.7 | 1 | 1.3 | k | 7 | |
| Bias resistor ratio R2/R1 (PDTB113ZU) | R2/R1 | 9 | 10 | 11 | 7 |
CAD (KiCad official)
- Symbol:
PDTB113ZUX - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SOT-323-3 (KiCad packages3D, STEP)
- 3D model files:
pdtb113zux-etched.step/pdtb113zux-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pdtb113zux.step/pdtb113zux.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (27 pp, sha256
aeb51000de7ff915, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).