component

HEF4046BT

Public Made by Adom

by adom

Nexperia Clock Generators / Frequency Synthesizers / PLL, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timinghef4046btfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

HEF4046BT

Nexperia · Clock Generators / Frequency Synthesizers / PLL · SOIC-16

HEF4046BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PCP_OUT output Phase comparator pulse output, which is HIGH when phase comparator 2 is in its locked (high-impedance OFF) state and can indicate a locked condition.
2 PC1_OUT output Phase comparator 1 (EXCLUSIVE-OR) output, whose average voltage is 0.5VDD when there is no signal or noise at the signal input.
3 COMP_IN input Comparator input, connected directly or via a frequency divider to VCO_OUT, with HIGH-level input voltage of 3.5 V min at VDD = 5 V when DC coupled.
4 VCO_OUT output VCO output with a typical 50% duty factor, connected directly or via a frequency divider to COMP_IN.
5 INH input Inhibit input where LOW enables the VCO and source follower and HIGH turns both off to minimize standby power consumption.
6 C1A passive Capacitor C1 connection A, with C1 recommended from 50 pF upward to set the VCO frequency range together with R1.
7 C1B passive Capacitor C1 connection B, with C1 recommended from 50 pF upward to set the VCO frequency range together with R1.
8 VSS power_in Ground supply voltage (0 V reference).
9 VCO_IN input VCO input with a typical input resistance of 10 MΩ, fed by the low-pass filter and set to 0.5VDD for the center frequency.
10 SF_OUT output Source-follower output of the VCO input voltage, which needs a load resistor RL to VSS if used and should be left open if unused.
11 R1 passive Resistor R1 connection, which with C1 sets the VCO frequency range, with a recommended range of 10 kΩ to 1 MΩ.
12 R2 passive Resistor R2 connection, which sets an optional VCO frequency offset, with a recommended range of 10 kΩ to 1 MΩ.
13 PC2_OUT tri_state Phase comparator 2 3-state output that drives to VDD or VSS or goes high-impedance when locked.
14 SIG_IN input Signal input that can be direct-coupled with standard HEF4000B logic levels or capacitively coupled to the self-biasing amplifier for smaller swings.
15 ZENER passive Zener diode input for regulated supply, with a typical working voltage of 7.3 V at IZ = 50 μA, and left open when unused.
16 VDD power_in Supply voltage from 3.0 V to 15.0 V (absolute maximum 18 V), with PLL operation requiring 5 V to 15 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 6
Input clamping current IIK -10 10 mA VI < -0.5 V or VI > VDD + 0.5 V 6
Input voltage VI -0.5 0.5 V max is VDD + 0.5 V 6
Output clamping current IOK -10 10 mA VO < -0.5 V or VO > VDD + 0.5 V 6
Input/output current II/O -10 10 mA 6
Supply current IDD 50 mA 6
Storage temperature Tstg -65 150 °C 6
Ambient temperature Tamb -40 85 °C 6
Total power dissipation Ptot 500 mW -40 °C to +85 °C 6
Power dissipation per output P 100 mW 6
Supply voltage VDD 3 15 V 7
Supply voltage, fixed oscillator only VDD 3 15 V as fixed oscillator only 7
Supply voltage, PLL operation VDD 5 15 V phase-locked loop operation 7
Input voltage VI 0 15 V max is VDD 7
Ambient temperature Tamb -40 85 °C in free air 7
Input transition rise and fall rate Δt/ΔV 3.75 μs/V for INH input; VDD = 5 V 7
Input transition rise and fall rate Δt/ΔV 0.5 μs/V for INH input; VDD = 10 V 7
Input transition rise and fall rate Δt/ΔV 0.08 μs/V for INH input; VDD = 15 V 7
HIGH-level input voltage VIH 3.5 V /IO/ < 1 μA; VDD = 5 V; Tamb = -40/+25/+85 °C 7
HIGH-level input voltage VIH 7 V /IO/ < 1 μA; VDD = 10 V; Tamb = -40/+25/+85 °C 7
HIGH-level input voltage VIH 11 V /IO/ < 1 μA; VDD = 15 V; Tamb = -40/+25/+85 °C 7
LOW-level input voltage VIL 1.5 V /IO/ < 1 μA; VDD = 5 V; Tamb = -40/+25/+85 °C 7
LOW-level input voltage VIL 3 V /IO/ < 1 μA; VDD = 10 V; Tamb = -40/+25/+85 °C 7
LOW-level input voltage VIL 4 V /IO/ < 1 μA; VDD = 15 V; Tamb = -40/+25/+85 °C 7
HIGH-level output voltage VOH 4.95 V /IO/ < 1 μA; VDD = 5 V; Tamb = -40/+25/+85 °C 7
HIGH-level output voltage VOH 9.95 V /IO/ < 1 μA; VDD = 10 V; Tamb = -40/+25/+85 °C 7
HIGH-level output voltage VOH 14.95 V /IO/ < 1 μA; VDD = 15 V; Tamb = -40/+25/+85 °C 7
LOW-level output voltage VOL 0.05 V /IO/ < 1 μA; VDD = 5/10/15 V; Tamb = -40/+25/+85 °C 7
HIGH-level output current IOH -1.4 mA VO = 2.5 V; VDD = 5 V; Tamb = +25 °C 7
HIGH-level output current IOH -0.44 mA VO = 4.6 V; VDD = 5 V; Tamb = +25 °C 7
HIGH-level output current IOH -1.1 mA VO = 9.5 V; VDD = 10 V; Tamb = +25 °C 7
HIGH-level output current IOH -3 mA VO = 13.5 V; VDD = 15 V; Tamb = +25 °C 7
LOW-level output current IOL 0.44 mA VO = 0.4 V; VDD = 5 V; Tamb = +25 °C 7
LOW-level output current IOL 1.1 mA VO = 0.5 V; VDD = 10 V; Tamb = +25 °C 7
LOW-level output current IOL 3 mA VO = 1.5 V; VDD = 15 V; Tamb = +25 °C 7
Input leakage current II -0.3 0.3 μA VDD = 15 V; Tamb = +25 °C 7
Input leakage current II -1 1 μA VDD = 15 V; Tamb = +85 °C 7
OFF-state output current, output HIGH IOZ 1.6 μA output HIGH and returned to VDD; VDD = 15 V; Tamb = +25 °C 7
OFF-state output current, output LOW IOZ 1.6 μA output LOW and returned to VSS; VDD = 15 V; Tamb = +25 °C 7
Supply current IDD 20 μA IO = 0 A; VDD = 5 V; [2]; Tamb = +25 °C 8
Supply current IDD 40 μA IO = 0 A; VDD = 10 V; [2]; Tamb = +25 °C 8
Supply current IDD 80 μA IO = 0 A; VDD = 15 V; [2]; Tamb = +25 °C 8
Supply current IDD 150 μA IO = 0 A; VDD = 5 V; [2]; Tamb = +85 °C 8
Supply current IDD 600 μA IO = 0 A; VDD = 15 V; [2]; Tamb = +85 °C 8
Input capacitance CI 7.5 pF for INH input 8
Input resistance SIG_IN RI 750 kΩ SIG_IN input; at self-bias operating point; VDD = 5 V 8
LOW-level input voltage SIG_IN/COMP_IN VIL 1.5 V DC coupled LOW; full temperature range; VDD = 5 V 8
HIGH-level input voltage SIG_IN/COMP_IN VIH 3.5 V DC coupled HIGH; full temperature range; VDD = 5 V 8
Maximum VCO frequency fmax 0.5 1 MHz VCO_IN at VDD; R1 = 10 kΩ; R2 = ∞; C1 = 50 pF; VDD = 5 V 9
Maximum VCO frequency fmax 1 2 MHz VCO_IN at VDD; R1 = 10 kΩ; R2 = ∞; C1 = 50 pF; VDD = 10 V 9
Maximum VCO frequency fmax 1.3 2.7 MHz VCO_IN at VDD; R1 = 10 kΩ; R2 = ∞; C1 = 50 pF; VDD = 15 V 9
Zener working voltage VZ 7.3 V IZ = 50 μA 9
Zener dynamic resistance Rdyn 25 Ω For internal zener diode; IZ = 1 mA 9
VCO power dissipation P 150 μW f0 = 10 kHz; R1 = 1 MΩ; R2 = ∞; VCO_IN at 0.5 VDD; VDD = 5 V 9
VCO duty factor δ 50 % VCO_OUT output; VDD = 5 V 9
VCO_IN input resistance Rin 10 MΩ pin VCO_IN 9

CAD (KiCad official)

  • Symbol: HEF4046BT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hef4046bt-etched.step / hef4046bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4046bt.step / hef4046bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 558bd23805a1d9bd, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF