TJA1050DRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXD	input	Transmit data input from the CAN controller. TTL/CMOS-compatible input (VIH ≥ 2 V, VIL ≤ 0.8 V, tolerant to VCC+0.3 V). Driving low forces a dominant bit on the bus; high (or floating with internal pull-up) leaves the bus recessive.
2	GND	power_in	Device ground reference. Connect to the system 0 V rail.
3	VCC	power_in	Supply voltage input, 4.75 V to 5.25 V nominal (absolute max −0.3 V to 6 V). Typical ICC ≈ 5 mA recessive / 50 mA dominant in normal mode and ≈10 µA in standby mode. Decouple locally with a 100 nF ceramic capacitor.
4	RXD	output	Receive data output to the CAN controller. Reports the bus state: LOW = dominant, HIGH = recessive. Push-pull output with VOH ≈ VCC−0.7 V at −100 µA and IOL sink capability of 6 mA typ.
5	SPLIT	output	Common-mode stabilization output, typically 0.5·VCC in normal mode (driving up to ±500 µA). Intended for connection to the mid-point of a split bus termination (two 60 Ω resistors) to improve EMC. High-impedance in standby mode; ±27 V DC tolerant.
6	CANL	bidirectional	Low-side CAN bus line. Dominant output ≈1.4 V (0.5-1.75 V); recessive ≈0.5·VCC. Withstands −27 V to +40 V DC and ISO 7637 transients to ±200 V; ESD ±6 kV HBM.
7	CANH	bidirectional	High-side CAN bus line. Dominant output ≈3.6 V (3.0-4.25 V); recessive ≈0.5·VCC. Withstands −27 V to +40 V DC and ISO 7637 transients to ±200 V; ESD ±6 kV HBM.
8	STB	input	Standby-mode control input. LOW = normal (high-speed) mode; HIGH = low-current standby with bus wake-up detection. TTL/CMOS-compatible (VIH ≥ 2 V, VIL ≤ 0.8 V).

Key specifications

Parameter	Value
Manufacturer	HANSCHIP semiconductor
Package	SOP-8
Category	Comm/UART
Pins	8

Ordering variants

Same part, different packaging or reel option.

TJA1050DRG
TJA1050DRGDGKRG

CAD (KiCad official)

Symbol: TJA1050DRG
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tja1050drg.step`	122 KB	You want the bare part, or you mark your own boards.
`tja1050drg-etched.step`	2.1 MB	You want the part with `TJA1050DRG` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 518 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HANSCHIP semiconductor datasheet (11 pp, sha256 510a842962d0cdd8, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF