DS16EV5110ASQE from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	C_IN-	input	Inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω terminating resistor to VDD.
2	C_IN+	input	Non-inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω terminating resistor to VDD.
3	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
4	D_IN0-	input	Inverting TMDS data channel 0 input (CML) with an on-chip 50Ω terminating resistor to VDD.
5	D_IN0+	input	Non-inverting TMDS data channel 0 input (CML) with an on-chip 50Ω terminating resistor to VDD.
6	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
7	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
8	D_IN1-	input	Inverting TMDS data channel 1 input (CML) with an on-chip 50Ω terminating resistor to VDD.
9	D_IN1+	input	Non-inverting TMDS data channel 1 input (CML) with an on-chip 50Ω terminating resistor to VDD.
10	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
11	D_IN2-	input	Inverting TMDS data channel 2 input (CML) with an on-chip 50Ω terminating resistor to VDD.
12	D_IN2+	input	Non-inverting TMDS data channel 2 input (CML) with an on-chip 50Ω terminating resistor to VDD.
13	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
14	BST_1	input	LVCMOS equalizer boost select bit 1 (BST_[0:2] select boost level, internally pulled Low).
15	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
16	CS	input	SMBus chip select: High enables the SMBus register, Low disables it; internally pulled Low and gated with SDC.
17	SDC	input	SMBus clock input, 3.3V LVCMOS (not 5V tolerant), internally pulled High to 3.3V with a High-Z pull-up.
18	SDA	bidirectional	SMBus data input/output, 3.3V LVCMOS (not 5V tolerant), internally pulled High to 3.3V with a High-Z pull-up.
19	Reserv	unconnected	Reserved; do not connect.
20	Reserv	unconnected	Reserved; do not connect.
21	FEB	input	Force External Boost: High selects boost control by BST_[0:2] pins, Low selects SMBus control; internally pulled High.
22	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
23	BST_0	input	LVCMOS equalizer boost select bit 0 (BST_[0:2] select boost level, internally pulled Low).
24	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
25	D_OUT2+	output	Non-inverting TMDS data channel 2 output (CML, open collector).
26	D_OUT2-	output	Inverting TMDS data channel 2 output (CML, open collector).
27	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
28	D_OUT1+	output	Non-inverting TMDS data channel 1 output (CML, open collector).
29	D_OUT1-	output	Inverting TMDS data channel 1 output (CML, open collector).
30	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
31	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
32	D_OUT0+	output	Non-inverting TMDS data channel 0 output (CML, open collector).
33	D_OUT0-	output	Inverting TMDS data channel 0 output (CML, open collector).
34	GND	power_in	Ground reference, tied to a solid ground plane through a low-impedance path.
35	C_OUT+	output	Non-inverting TMDS clock output (CML, open collector).
36	C_OUT-	output	Inverting TMDS clock output (CML, open collector).
37	BST_2	input	LVCMOS equalizer boost select bit 2 (BST_[0:2] select boost level, internally pulled Low).
38	Reserv	unconnected	Reserved; do not connect.
39	Reserv	unconnected	Reserved; do not connect.
40	Reserv	unconnected	Reserved; do not connect.
41	Reserv	unconnected	Reserved; do not connect.
42	Reserv	unconnected	Reserved; do not connect.
43	Reserv	unconnected	Reserved; do not connect.
44	EN	input	Enable input, global to all channels: High selects normal operation, Low selects standby mode; internally pulled High.
45	SD	output	LVCMOS clock channel signal detect output, High when a signal is detected.
46	VDD	power_in	Power supply pin, tied to the VDD plane through a low-inductance path with a 0.1µF bypass capacitor to GND.
47	Reserv	unconnected	Reserved; do not connect.
48	Reserv	unconnected	Reserved; do not connect.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Interface
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD to GND)		3	3.3	3.6	V		4
Ambient Temperature		-40	25	85	°C		4
Supply Voltage (VDD)		-0.5		4	V		4
LVCMOS Input Voltage		-0.5		4	V		4
LVCMOS Output Voltage		-0.5		4	V		4
CML Input/Output Voltage		-0.5		4	V		4
Junction Temperature				150	°C		4
Storage Temperature		-65		150	°C		4
Lead Temperature (Soldering, 5 sec.)				260	°C	Soldering, 5 sec.	4
ESD Rating		6			kV	HBM, 1.5 kΩ, 100 pF	4
Thermal Resistance	θJA		30		°C/W	No Airflow	4
High Level Input Leakage Current (pull-up pins)	IIH-PU	-10		10	µA	LVCMOS pins with internal pull-up resistors	4
High Level Input Leakage Current (pull-down pins)	IIH-PD	80		105	µA	LVCMOS pins with internal pull-down resistors	4
Low Level Input Leakage Current (pull-up pins)	IIL-PU	-20		-10	µA	LVCMOS pins with internal pull-up resistors	4
Low Level Input Leakage Current (pull-down pins)	IIL-PD	-10		10	µA	LVCMOS pins with internal pull-down resistors	4
High Level Input Voltage	VIH	2			V		4
Low Level Input Voltage	VIL	0		0.8	V		4
High Level Output Voltage	VOH	2.4			V	SD Pin, IOH = -3mA	4
Low Level Output Voltage	VOL			0.4	V	SD Pin, IOL = 3mA	4
Power Dissipation	PD		475	700	mW	EN = High, Device Enabled	4
Input Voltage Swing (Launch Amplitude)	VTX	800		1200	mVP-P	Measured differentially at TPA (Figure 2)	5
Input Resistance	RIN	45	50	55	Ω	IN+ to VDD and IN− to VDD	5
Output Voltage Swing	VO	800		1200	mVP-P	Measured differentially with OUT+ and OUT− terminated by 50Ω to VDD	5
Output Leakage Current	IOFF	-1		1	µA	VOUT = 3.6V, VDD = open or 0V	5
Transition Time	tR, tF	75		240	ps	20% to 80% of differential output voltage, measured within 1" from output pins.	5
Total Jitter at 1.65 Gbps	TJ1		0.13	0.17	UIP-P	20m 28 AWG STP DVI Cable, EQ Setting 0x04, PRBS7	5
Clock Frequency	FCLK	25		225	MHz	Clock Path	5
Bit Rate	BR	0.25		2.25	Gbps	Data Path	5
Data, Clock Input High Voltage (SMBus)	VIH	2.8			V		6
Nominal Bus Voltage	VDD	3		3.6	V		6
Input Leakage per bus segment	ILEAK-Bus	-200		200	µA	per bus segment	6
Bus Operating Frequency	FSMB	10		100	kHz		6
Detect Clock Low Timeout	TTIMEOUT	25		35	ms		6
Clock High Period	THIGH	4		50	µs		6

CAD (KiCad official)

Symbol: DS16EV5110ASQE
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ds16ev5110asqe-etched.step / ds16ev5110asqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds16ev5110asqe.step / ds16ev5110asqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 8197f99e1a4a9be5, retrieved 2026-11-10, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS16EV5110ASQE

Verified DS16EV5110ASQE

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README