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AD7997BRUZ-0REEL
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Analog Devices Analog To Digital Converters (ADCs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD7997BRUZ-0REEL
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-20
AD7997BRUZ-0REEL from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground reference for all circuitry; all analog input signals should be referred to this AGND voltage. |
| 2 | VDD | power_in | Power supply input with a VDD range of 2.7 V to 5.5 V. |
| 3 | AGND | power_in | Analog ground reference for all circuitry; all analog input signals should be referred to this AGND voltage. |
| 4 | AGND | power_in | Analog ground reference for all circuitry; all analog input signals should be referred to this AGND voltage. |
| 5 | VDD | power_in | Power supply input with a VDD range of 2.7 V to 5.5 V. |
| 6 | REFIN | input | External voltage reference input with a range of 1.2 V to VDD, with 0.1 µF and 1 µF capacitors placed between REFIN and AGND. |
| 7 | VIN1 | input | Analog input 1, a single-ended channel with an input range of 0 V to REFIN. |
| 8 | VIN3 | input | Analog input 3, a single-ended channel with an input range of 0 V to REFIN. |
| 9 | VIN5 | input | Analog input 5, a single-ended channel with an input range of 0 V to REFIN. |
| 10 | VIN7 | input | Analog input 7, a single-ended channel with an input range of 0 V to REFIN. |
| 11 | VIN8 | input | Analog input 8, a single-ended channel with an input range of 0 V to REFIN. |
| 12 | VIN6 | input | Analog input 6, a single-ended channel with an input range of 0 V to REFIN. |
| 13 | VIN4 | input | Analog input 4, a single-ended channel with an input range of 0 V to REFIN. |
| 14 | VIN2 | input | Analog input 2, a single-ended channel with an input range of 0 V to REFIN. |
| 15 | AS | input | Address select logic input that selects one of three I2C addresses, depending on the voltage applied to the pin (Table 6). |
| 16 | CONVST | input | Edge-triggered convert start input: the rising edge powers up the part (1 µs power-up time) and the falling edge places the track/hold into hold mode and initiates a conversion. |
| 17 | ALERT/BUSY | output | Open-drain digital output selectable as an ALERT out-of-range indicator or a BUSY indicator that is active while a conversion is in progress. |
| 18 | SDA | bidirectional | Serial bus bidirectional data line with an open-drain output, requiring an external pull-up resistor. |
| 19 | SCL | input | Serial bus clock, an open-drain input requiring an external pull-up resistor. |
| 20 | AGND | power_in | Analog ground reference for all circuitry; all analog input signals should be referred to this AGND voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20 |
| Category | Data Converters |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal to Noise and Distortion (SINAD) | SINAD | 61 | dB | FIN = 1 kHz sine wave for fSCL up to 400 kHz | 3 | ||
| Total Harmonic Distortion | THD | -75 | dB | FIN = 1 kHz sine wave for fSCL up to 400 kHz | 3 | ||
| Peak Harmonic or Spurious Noise | SFDR | -76 | dB | FIN = 1 kHz sine wave for fSCL up to 400 kHz | 3 | ||
| Integral Nonlinearity | INL | -0.5 | 0.5 | LSB | 3 | ||
| Differential Nonlinearity | DNL | -0.5 | 0.5 | LSB | Guaranteed no missed codes to 10 bits | 3 | |
| Offset Error | -1.5 | 1.5 | LSB | Mode 1 (CONVST Mode) | 3 | ||
| Offset Error | -2.5 | 2.5 | LSB | Mode 2 (Command Mode) | 3 | ||
| Offset Error Match | -0.5 | 0.5 | LSB | 3 | |||
| Gain Error | -1.5 | 1.5 | LSB | 3 | |||
| Gain Error Match | -0.5 | 0.5 | LSB | 3 | |||
| DC Leakage Current (analog input) | -1 | 1 | µA | 3 | |||
| REFIN Input Voltage Range | 1.2 | V | Maximum is VDD | 3 | |||
| DC Leakage Current (REFIN) | -1 | 1 | µA | 3 | |||
| Input High Voltage | VINH | 0.7 | V | Printed as 0.7 (VDD) V min, logic inputs SDA, SCL | 3 | ||
| Input Low Voltage | VINL | 0.3 | V | Printed as 0.3 (VDD) V max, logic inputs SDA, SCL | 3 | ||
| Input Leakage Current | IIN | -1 | 1 | µA | VIN = 0 V or VDD | 3 | |
| Input Capacitance | CIN | 10 | pF | Logic inputs SDA, SCL | 3 | ||
| Input Hysteresis | VHYST | 0.1 | V | Printed as 0.1 (VDD) V min | 3 | ||
| Fall time of SDA signal, standard mode | t10 | 300 | ns | Standard mode | 8 | ||
| Fall time of SDA signal, fast mode | t10 | 300 | ns | Fast mode, 20 + 0.1 CB | 8 | ||
| Rise time of SCL signal, standard mode | t11 | 1000 | ns | Standard mode | 8 | ||
| Rise time of SCL signal, fast mode | t11 | 300 | ns | Fast mode, 20 + 0.1 CB | 8 | ||
| Rise time of SCL signal after repeated start and after Acknowledge, standard mode | t11A | 1000 | ns | Standard mode | 8 | ||
| Rise time of SCL signal after repeated start and after Acknowledge, fast mode | t11A | 300 | ns | Fast mode, 20 + 0.1 CB | 8 | ||
| Fall time of SCL signal, standard mode | t12 | 300 | ns | Standard mode | 8 | ||
| Fall time of SCL signal, fast mode | t12 | 300 | ns | Fast mode, 20 + 0.1 CB | 8 | ||
| Pulse width of suppressed spike | tSP | 0 | 50 | ns | Fast mode | 8 | |
| VDD to GND | VDD | -0.3 | 7 | V | 9 | ||
| Analog Input Voltage to GND | -0.3 | V | Maximum printed as VDD + 0.3 V | 9 | |||
| Reference Input Voltage to GND | -0.3 | V | Maximum printed as VDD + 0.3 V | 9 | |||
| Digital Input Voltage to GND | -0.3 | 7 | V | 9 | |||
| Digital Output Voltage to GND | -0.3 | V | Maximum printed as VDD + 0.3 V | 9 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | Transient currents up to 100 mA do not cause SCR latch-up | 9 | ||
| Operating Temperature Range (Commercial, B Version) | -40 | 85 | °C | 9 | |||
| Storage Temperature Range | -65 | 150 | °C | 9 | |||
| Junction Temperature | 150 | °C | 9 | ||||
| Thermal Impedance θJA | θJA | 143 | °C/W | 20-Lead TSSOP | 9 | ||
| Thermal Impedance θJC | θJC | 45 | °C/W | 20-Lead TSSOP | 9 | ||
| ESD | 1.5 | kV | 9 | ||||
| Supply voltage VDD | VDD | 2.7 | 5.5 | V | VDD range for the AD7997/AD7998 per pin function description | 10 |
CAD (KiCad official)
- Symbol:
AD7997BRUZ-0REEL - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ad7997bruz-0reel-etched.step/ad7997bruz-0reel-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7997bruz-0reel.step/ad7997bruz-0reel.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
081ef00889049a99, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).