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TMS320F2809PZS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F2809PZS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F2809PZS from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12 bidirectional General-purpose I/O 12 (I/O/Z) with trip zone input 1, CAN-B transmit and SPI-B slave-in/master-out alternate functions; pullup is enabled at reset.
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin (3.3 V).
4 GPIO29 bidirectional General-purpose I/O 29 with an 8-mA (typical) output buffer; alternate functions are SCI-A transmit data and trip zone 6 input.
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (I/O/Z); alternate functions are I2C clock open-drain port, ePWM external sync output and ADC start-of-conversion B output.
6 GPIO30/CANRXA bidirectional General-purpose I/O 30 with an 8-mA (typical) output buffer; alternate function is enhanced CAN-A receive data.
7 GPIO31/CANTXA bidirectional General-purpose I/O 31 with an 8-mA (typical) output buffer; alternate function is enhanced CAN-A transmit data.
8 GPIO14 bidirectional General-purpose I/O 14 (I/O/Z); alternate functions are trip zone input 3, SCI-B transmit and SPI-B clock input/output.
9 GPIO15 bidirectional General-purpose I/O 15 (I/O/Z); alternate functions are trip zone input 4, SCI-B receive and SPI-B slave transmit enable.
10 VDD power_in CPU and logic digital power pin (1.8 V).
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin (1.8 V).
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin (3.3 V).
16 ADCINA7 input ADC Group A channel 7 analog input, 0 to 3 V with respect to ADCLO.
17 ADCINA6 input ADC Group A channel 6 analog input, 0 to 3 V with respect to ADCLO.
18 ADCINA5 input ADC Group A channel 5 analog input, 0 to 3 V with respect to ADCLO.
19 ADCINA4 input ADC Group A channel 4 analog input, 0 to 3 V with respect to ADCLO.
20 ADCINA3 input ADC Group A channel 3 analog input, 0 to 3 V with respect to ADCLO.
21 ADCINA2 input ADC Group A channel 2 analog input, 0 to 3 V with respect to ADCLO.
22 ADCINA1 input ADC Group A channel 1 analog input, 0 to 3 V with respect to ADCLO.
23 ADCINA0 input ADC Group A channel 0 analog input, 0 to 3 V with respect to ADCLO.
24 ADCLO input ADC low reference, to be connected to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin (3.3 V).
27 ADCINB0 input ADC Group B channel 0 analog input, 0 to 3 V with respect to ADCLO.
28 ADCINB1 input ADC Group B channel 1 analog input, 0 to 3 V with respect to ADCLO.
29 ADCINB2 input ADC Group B channel 2 analog input, 0 to 3 V with respect to ADCLO.
30 ADCINB3 input ADC Group B channel 3 analog input, 0 to 3 V with respect to ADCLO.
31 ADCINB4 input ADC Group B channel 4 analog input, 0 to 3 V with respect to ADCLO.
32 ADCINB5 input ADC Group B channel 5 analog input, 0 to 3 V with respect to ADCLO.
33 ADCINB6 input ADC Group B channel 6 analog input, 0 to 3 V with respect to ADCLO.
34 ADCINB7 input ADC Group B channel 7 analog input, 0 to 3 V with respect to ADCLO.
35 ADCREFIN input External ADC reference input.
36 ADCREFM output Internal ADC reference medium output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and must not be externally loaded.
37 ADCREFP output Internal ADC reference positive output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and must not be externally loaded.
38 ADCRESEXT passive ADC external current bias resistor; connect a 22-kΩ resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin (1.8 V).
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin (1.8 V).
43 GPIO34 bidirectional General-purpose I/O 34 (I/O/Z) with no peripheral alternate function listed; pullup is enabled at reset.
44 GPIO1/EPWM1B/SPISIMOD bidirectional General-purpose I/O 1 (I/O/Z) with ePWM1 output B and SPI-D slave-in/master-out alternate functions; pullup is not enabled at reset.
45 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (I/O/Z) with ePWM2 output A and HRPWM channel alternate function; pullup is not enabled at reset.
46 VDDIO power_in Digital I/O power pin (3.3 V).
47 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (I/O/Z) with ePWM1 output A and HRPWM channel alternate function; pullup is not enabled at reset.
48 GPIO3/EPWM2B/SPISOMID bidirectional General-purpose I/O 3 (I/O/Z) with ePWM2 output B and SPI-D slave-out/master-in alternate functions; pullup is not enabled at reset.
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/CANTXB/TZ5 bidirectional General-purpose I/O 16 (I/O/Z) with SPI-A slave-in/master-out, enhanced CAN-B transmit and trip zone 5 input alternate functions; pullup is enabled at reset.
51 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (I/O/Z) with ePWM3 output A and HRPWM channel alternate function; pullup is not enabled at reset.
52 GPIO17/SPISOMIA/CANRXB/TZ6 bidirectional General-purpose I/O 17 (I/O/Z) with SPI-A slave-out/master-in, enhanced CAN-B receive and trip zone 6 input alternate functions; pullup is enabled at reset.
53 GPIO5/EPWM3B/SPICLKD/ECAP1 bidirectional General-purpose I/O 5 (I/O/Z) with ePWM3 output B, SPI-D clock and enhanced capture 1 alternate functions; pullup is not enabled at reset.
54 GPIO18/SPICLKA/SCITXDB bidirectional General-purpose I/O 18 (I/O/Z) with SPI-A clock input/output and SCI-B transmit alternate functions; pullup is enabled at reset.
55 VSS power_in Digital ground pin.
56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (I/O/Z) with ePWM4 output A and HRPWM channel, external ePWM sync input and sync output alternate functions; pullup is not enabled at reset.
57 GPIO19/SPISTEA/SCIRXDB bidirectional General-purpose I/O 19 (I/O/Z) with SPI-A slave transmit enable and SCI-B receive alternate functions; pullup is enabled at reset.
58 GPIO7/EPWM4B/SPISTED/ECAP2 bidirectional General-purpose I/O 7 (I/O/Z) with ePWM4 output B, SPI-D slave transmit enable and enhanced capture 2 alternate functions; pullup is not enabled at reset.
59 VDD power_in CPU and logic digital power pin (1.8 V).
60 GPIO8/EPWM5A/CANTXB/ADCSOCAO bidirectional General-purpose I/O 8 (I/O/Z) with ePWM5 output A and HRPWM channel, enhanced CAN-B transmit and ADC start-of-conversion A output alternate functions; pullup is not enabled at reset.
61 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose I/O 9 (I/O/Z) with ePWM5 output B, SCI-B transmit and enhanced capture 3 alternate functions; pullup is not enabled at reset.
62 VSS power_in Digital ground pin.
63 GPIO20/EQEP1A/SPISIMOC/CANTXB bidirectional General-purpose I/O 20 (I/O/Z) with enhanced QEP1 input A, SPI-C slave-in/master-out and enhanced CAN-B transmit alternate functions; pullup is enabled at reset.
64 GPIO10/EPWM6A/CANRXB/ADCSOCBO bidirectional General-purpose I/O 10 (I/O/Z) with ePWM6 output A and HRPWM channel, enhanced CAN-B receive and ADC start-of-conversion B output alternate functions; pullup is not enabled at reset.
65 VDDIO power_in Digital I/O power pin (3.3 V).
66 XCLKOUT output Output clock derived from SYSCLKOUT at the same, half or quarter frequency (XCLKOUTDIV); reset value is SYSCLKOUT/4 and it is not placed in high impedance during reset (8-mA drive).
67 GPIO21/EQEP1B/SPISOMIC/CANRXB bidirectional General-purpose I/O 21 (I/O/Z) with enhanced QEP1 input B, SPI-C master-in/slave-out and enhanced CAN-B receive alternate functions; pullup is enabled at reset.
68 VDD power_in CPU and logic digital power pin (1.8 V).
69 VSS power_in Digital ground pin.
70 GPIO11/EPWM6B/SCIRXDB/ECAP4 bidirectional General-purpose I/O 11 (I/O/Z) with ePWM6 output B, SCI-B receive and enhanced capture 4 alternate functions; pullup is not enabled at reset.
71 GPIO22/EQEP1S/SPICLKC/SCITXDB bidirectional General-purpose I/O 22 (I/O/Z) with enhanced QEP1 strobe, SPI-C clock and SCI-B transmit alternate functions; pullup is enabled at reset.
72 GPIO23/EQEP1I/SPISTEC/SCIRXDB bidirectional General-purpose I/O 23 (I/O/Z) with enhanced QEP1 index, SPI-C slave transmit enable and SCI-B receive alternate functions; pullup is enabled at reset.
73 TDI input JTAG test data input, clocked into the selected register on a rising edge of TCK; internal pullup.
74 TMS input JTAG test-mode select, clocked into the TAP controller on the rising edge of TCK; internal pullup.
75 TCK input JTAG test clock; internal pullup.
76 TDO tri_state JTAG scan out test data output, shifted out on the falling edge of TCK (O/Z, 8-mA drive).
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal pullup, driven low for 512 OSCCLK cycles during a watchdog reset.
79 GPIO27/ECAP4/EQEP2S/SPISTEB bidirectional General-purpose I/O 27 (I/O/Z) with enhanced capture 4, enhanced QEP2 strobe and SPI-B slave transmit enable alternate functions; pullup is enabled at reset.
80 EMU0 bidirectional Emulator pin 0 used for emulator interrupt input/output and boundary-scan mode entry; 8-mA drive with internal pullup, and an external 2.2-kΩ to 4.7-kΩ pullup is recommended.
81 EMU1 bidirectional Emulator pin 1 used for emulator interrupt input/output and boundary-scan mode entry; 8-mA drive with internal pullup, and an external 2.2-kΩ to 4.7-kΩ pullup is recommended.
82 VDDIO power_in Digital I/O power pin (3.3 V).
83 GPIO24/ECAP1/EQEP2A/SPISIMOB bidirectional General-purpose I/O 24 (I/O/Z) with enhanced capture 1, enhanced QEP2 input A and SPI-B slave-in/master-out alternate functions; pullup is enabled at reset.
84 TRST input JTAG test reset with internal pulldown; must be held low during normal operation and an external 2.2-kΩ pulldown is recommended.
85 VDD power_in CPU and logic digital power pin (1.8 V).
86 X2 output Internal oscillator output; a quartz crystal or ceramic resonator connects across X1 and X2, and X2 must be left unconnected if unused.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input referenced to the 1.8-V core supply; a 1.8-V external oscillator may drive it with XCLKIN tied to ground.
89 VSS power_in Analog ground pin (VSSA ground via dedicated package pin).
90 XCLKIN input External oscillator input for a 3.3-V oscillator; tie X1 to GND in that case, or tie XCLKIN to GND when a crystal or 1.8-V oscillator on X1 is used.
91 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose I/O 25 (I/O/Z) with enhanced capture 2, enhanced QEP2 input B and SPI-B master-in/slave-out alternate functions; pullup is enabled at reset.
92 GPIO28/SCIRXDA/TZ5 bidirectional General-purpose I/O 28 with an 8-mA (typical) output buffer; alternate functions are SCI-A receive data and trip zone 5 input.
93 VDD power_in CPU and logic digital power pin (1.8 V).
94 VSS power_in Digital ground pin.
95 GPIO13 bidirectional General-purpose I/O 13 (I/O/Z) with trip zone input 2, enhanced CAN-B receive and SPI-B slave-out/master-in alternate functions; pullup is enabled at reset.
96 VDD3VFL power_in 3.3-V flash core power pin that must be connected to 3.3 V at all times.
97 TEST1 bidirectional Test pin reserved for TI; must be left unconnected.
98 TEST2 bidirectional Test pin reserved for TI; must be left unconnected.
99 GPIO26/ECAP3/EQEP2I/SPICLKB bidirectional General-purpose I/O 26 (I/O/Z) with enhanced capture 3, enhanced QEP2 index and SPI-B clock alternate functions; pullup is enabled at reset.
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 (I/O/Z) with I2C data open-drain port, external ePWM sync input and ADC start-of-conversion A output alternate functions; pullup is enabled at reset.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F2809PZS
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2809pzs-etched.step / tms320f2809pzs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2809pzs.step / tms320f2809pzs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF