component
XL3842
Public Made by Adomby adom
XINLUDA AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXL3842
XINLUDA · AC-DC Controllers And Regulators · SOP-8
XL3842 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | This pin is the Error Amplifier output and is made available for loop compensation. |
| 2 | VFB | input | This is the inverting input of the Error Amplifier, normally connected to the switching power supply output through a resistor divider. |
| 3 | ISENSE | input | A voltage proportional to inductor current is connected to this input, and the PWM uses it to terminate the output switch conduction. |
| 4 | RT/CT | passive | Resistor RT connects to Vref and capacitor CT to ground to program the oscillator frequency and maximum output duty cycle, and operation to 500kHz is possible. |
| 5 | GROUND | power_in | This pin is the combined control circuitry and power ground. |
| 6 | OUTPUT | output | This output directly drives the gate of a power MOSFET, sourcing and sinking peak currents up to 1A. |
| 7 | VCC | power_in | This pin is the positive supply of the control IC, with a recommended supply voltage of 12 to 28 V. |
| 8 | VREF | power_out | This is the reference output that provides charging current for capacitor CT through resistor RT. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (low impedance source) | Vi | 30 | V | low impedance source | 4 | ||
| Output Current | IO | 1 | A | 4 | |||
| Output Energy (capacitive load) | EO | 5 | J | capacitive load | 4 | ||
| Analog Inputs (pins 2, 3) | -0.3 | 5.5 | V | pins 2, 3 | 4 | ||
| Error Amplifier Output Sink Current | 10 | mA | 4 | ||||
| Power Dissipation (SO8) | Ptot | 800 | mW | Tamb 25 C (SO8) | 4 | ||
| Storage Temperature Range | Tstg | -65 | 150 | C | 4 | ||
| Junction Operating Temperature | TJ | -40 | 150 | C | 4 | ||
| Lead Temperature | TL | 300 | C | soldering 10s | 4 | ||
| Supply voltage | VCC | 12 | 28 | V | 4 | ||
| Input voltage (VFB) | VFB | 2.5 | V | 4 | |||
| Input voltage (ISENSE) | VISENSE | 1 | V | 4 | |||
| Supply current, externally limited | IVCC | 25 | mA | externally limited | 4 | ||
| Average output current | IOUTPUT | 200 | mA | 4 | |||
| Reference output current | IVREF | -20 | mA | 4 | |||
| Oscillator frequency | fOSC | 100 | 500 | kHZ | 4 | ||
| Operating free-air temperature (384x) | TA | 0 | 70 | C | 384x (XL3842, 0 to 70 C) | 4 | |
| Thermal resistance junction-ambient (SOP8) | Rth j-amb | 150 | C/W | SOP8 column | 4 | ||
| VREF Output Voltage | VREF | 4.9 | 5 | 5.1 | V | Tj = 25C Io = 1mA | 5 |
| VREF Line Regulation | VREF | 8 | 20 | mV | 12V ≤ Vi ≤ 25V | 5 | |
| VREF Load Regulation | VREF | 8 | 25 | mV | 1 ≤ Io ≤ 20mA | 5 | |
| Total Output Variation | 4.82 | 5.18 | V | Line, Load, Temperature | 5 | ||
| Long Term Stability | 7 | 30 | mV | Tamb = 125C, 1000Hrs (note 2) | 5 | ||
| Output Short Circuit | ISC | -180 | -100 | -30 | mA | 5 | |
| Initial accuracy | fOSC | 38 | 52 | 65 | KHz | Tj = 25C | 5 |
| Frequency Change with Voltage | fOSC/V | 0.6 | 5 | % | VCC = 12V to 25V | 5 | |
| Discharge Current (TJ = 25C) | Idischg | 7.8 | 8.3 | 8.8 | mA | VOSC = 2V, TJ = 25°C | 5 |
| Discharge Current (TA = Tlow to Thigh) | Idischg | 7.6 | 8.8 | mA | VOSC = 2V, TA = Tlow to Thigh | 5 | |
| Error Amp Input Voltage | V2 | 2.42 | 2.5 | 2.58 | V | VPIN1 = 2.5V | 5 |
| Error Amp Input Bias Current | Ib | -0.1 | -2 | A | VFB = 5V | 5 | |
| Error Amp Open-Loop Gain | AVOL | 65 | 90 | dB | 2V ≤ Vo ≤ 4V | 5 | |
| Unity Gain Bandwidth | BW | 0.7 | 1 | MHz | TJ = 25°C | 5 | |
| Power Supply Rejection Ratio | PSRR | 60 | 70 | dB | 12V ≤ Vi ≤ 25V | 5 | |
| Error Amp Output Sink Current | Io | 2 | 6 | mA | VPIN2 = 2.7V, VPIN1 = 1.1V | 5 | |
| Error Amp Output Source Current | Io | -0.5 | -1 | mA | VPIN2 = 2.3V, VPIN1 = 5V | 5 | |
| VOUT High | VOUT | 5 | 6.2 | V | VPIN2 = 2.3V; RL = 15K to Ground | 5 | |
| VOUT Low | VOUT | 0.8 | 1.1 | V | VPIN2 = 2.7V; RL = 15K to Pin 8 | 5 | |
| Current Sense Gain | GV | 2.85 | 3 | 3.15 | V/V | note 3 & 4 | 5 |
| Maximum Input Signal | V3 | 0.9 | 1 | 1.1 | V | VPIN1 = 5V (note 3) | 5 |
| Current Sense Input Bias Current | Ib | -2 | -10 | A | 5 | ||
| Delay to Output | 150 | 300 | ns | 5 | |||
| Output Low Level (20mA) | VOL | 0.1 | 0.4 | V | ISINK = 20mA | 6 | |
| Output Low Level (200mA) | VOL | 1.6 | 2.2 | V | ISINK = 200mA | 6 | |
| Output High Level (20mA) | VOH | 13 | 13.5 | V | ISOURCE = 20mA | 6 | |
| Output High Level (200mA) | VOH | 12 | 13.5 | V | ISOURCE = 200mA | 6 | |
| UVLO Saturation | VOLS | 0.1 | 1.1 | V | VCC = 6V; ISINK = 1mA | 6 | |
| Rise Time | tr | 50 | 150 | ns | Tj = 25C CL = 1nF (2) | 6 | |
| Fall Time | tf | 50 | 150 | ns | Tj = 25C CL = 1nF (2) | 6 | |
| Start Threshold (X842/4) | 14.5 | 16 | 17.5 | V | X842/4 | 6 | |
| Min Operating Voltage After Turn-on (X842/4) | 8.5 | 10 | 11.5 | V | X842/4 | 6 | |
| Maximum Duty Cycle (X842/3) | 94 | 96 | 100 | % | X842/3 | 6 | |
| Minimum Duty Cycle | 0 | % | 6 | ||||
| Start-up Current | Ist | 0.3 | 0.5 | mA | VCC = 14V for X842/44 | 6 | |
| Operating Supply Current | Ii | 12 | 20 | mA | VPIN2 = VPIN3 = 0V | 6 |
CAD (KiCad official)
- Symbol:
XL3842 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
xl3842-etched.step/xl3842-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl3842.step/xl3842.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (17 pp, sha256
a79edbe66e256697, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).