component
DP83867IRRGZR
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDP83867IRRGZR
Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)
DP83867IRRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TD_P_A | passive | Differential transmit/receive signal pair A positive for 1000BASE-T MDI connection |
| 2 | TD_M_A | passive | Differential transmit/receive signal pair A negative for 1000BASE-T MDI connection |
| 3 | VDDA2P5 | power_in | 2.5V (±5%) analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 4 | TD_P_B | passive | Differential transmit/receive signal pair B positive for 1000BASE-T MDI connection |
| 5 | TD_M_B | passive | Differential transmit/receive signal pair B negative for 1000BASE-T MDI connection |
| 6 | VDD1P0 | power_in | 1.0V (+15.5%, -5%) core analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 7 | TD_P_C | passive | Differential transmit/receive signal pair C positive for 1000BASE-T MDI connection |
| 8 | TD_M_C | passive | Differential transmit/receive signal pair C negative for 1000BASE-T MDI connection |
| 9 | VDDA2P5 | power_in | 2.5V (±5%) analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 10 | TD_P_D | passive | Differential transmit/receive signal pair D positive for 1000BASE-T MDI connection |
| 11 | TD_M_D | passive | Differential transmit/receive signal pair D negative for 1000BASE-T MDI connection |
| 12 | RBIAS | passive | Bias resistor connection; connect 11kΩ ±1% resistor to ground per design requirements |
| 13 | VDDA1P8 | power_in | 1.8V (±5%) analog power supply; may be left floating or connected to external 1.8V source with 1µF and 0.1µF bypass capacitors per operating mode |
| 14 | XO | output | Crystal oscillator output for 25MHz crystal; leave floating if using external oscillator |
| 15 | XI | input | Crystal oscillator or 25MHz oscillator input (50ppm maximum frequency tolerance) |
| 16 | MDC | input | Management data clock for MDIO interface; maximum frequency 25MHz with no minimum requirement; supports IEEE 802.3 SMI protocol |
| 17 | MDIO | bidirectional | Bidirectional management data input/output for SMI access; requires external 1.5kΩ or 2.2kΩ pull-up resistor to VDDIO per IEEE specification |
| 18 | CLK_OUT | output | Selectable clock output; configurable to output 25MHz reference, 125MHz receive clock, or divided 25MHz via IO_MUX_CFG register (address 0x0170) |
| 19 | VDDIO | power_in | I/O power supply selectable as 3.3V, 2.5V, or 1.8V (±5%); each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 20 | JTAG_CLK | input | IEEE 1149.1 JTAG test clock input; maximum frequency 2.5MHz; all test logic inputs and outputs clock source controlled by test entity |
| 21 | JTAG_TDO | output | IEEE 1149.1 JTAG test data output; latest test results scanned out through this pin per IEEE standard |
| 22 | JTAG_TMS | input | IEEE 1149.1 JTAG test mode select input; provides timing control to TAP controller's 16-state FSM for selecting test instructions |
| 23 | JTAG_TDI | input | IEEE 1149.1 JTAG test data input; test data scanned into device through this pin per IEEE 1149.1 standard |
| 24 | VDD1P0 | power_in | 1.0V (+15.5%, -5%) core analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 25 | TX_D3 | input | Transmit data bit 3 for GMII/RGMII/MII modes; synchronized to GTX_CLK in GMII/RGMII or TX_CLK in MII; active per MAC layer requirements |
| 26 | TX_D2 | input | Transmit data bit 2 for GMII/RGMII/MII modes; synchronized to GTX_CLK in GMII/RGMII or TX_CLK in MII; active per MAC layer requirements |
| 27 | TX_D1 | input | Transmit data bit 1 for GMII/RGMII/MII modes; synchronized to GTX_CLK in GMII/RGMII or TX_CLK in MII; active per MAC layer requirements |
| 28 | TX_D0 | input | Transmit data bit 0 for GMII/RGMII/MII modes; synchronized to GTX_CLK in GMII/RGMII or TX_CLK in MII; active per MAC layer requirements |
| 29 | GTX_CLK | input | GMII and RGMII transmit clock input from MAC; nominal frequency 125MHz for gigabit operation; externally supplied continuous clock signal |
| 30 | VDDIO | power_in | I/O power supply selectable as 3.3V, 2.5V, or 1.8V (±5%); each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 31 | VDD1P0 | power_in | 1.0V (+15.5%, -5%) core analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 32 | RX_CLK | output | Recovered receive clock output; 2.5MHz for 10Mbps, 25MHz for 100Mbps, 125MHz for 1000Mbps GMII/RGMII modes |
| 33 | RX_D0 | output | Receive data bit 0 for GMII/RGMII/MII modes; synchronized to RX_CLK; active when valid data present per operating mode |
| 34 | RX_D1 | output | Receive data bit 1 for GMII/RGMII/MII modes; synchronized to RX_CLK; active when valid data present per operating mode |
| 35 | RX_D2 | output | Receive data bit 2 for GMII/RGMII/MII modes; synchronized to RX_CLK; active when valid data present per operating mode |
| 36 | RX_D3 | output | Receive data bit 3 for GMII/RGMII/MII modes; synchronized to RX_CLK; active when valid data present per operating mode |
| 37 | TX_CTRL | input | Transmit control signal for RGMII mode multiplexing GMII TX_EN and TX_ER using dual clock edges on GTX_CLK for low power operation |
| 38 | RX_CTRL | output | Receive control signal for RGMII mode multiplexing GMII RX_DV and RX_ER using dual clock edges on RX_CLK for valid data indication |
| 39 | GPIO_1 | bidirectional | Configurable general-purpose I/O pin #1; supports multiplexed functions via GPIO_MUX_CTRL2 register (address 0x0172) including WoL, 1588 SFD, LED, and PRBS status |
| 40 | GPIO_0 | bidirectional | Configurable general-purpose I/O pin #0; supports multiplexed functions via GPIO_MUX_CTRL2 register (address 0x0172) including WoL, 1588 SFD, LED, and PRBS status |
| 41 | VDDIO | power_in | I/O power supply selectable as 3.3V, 2.5V, or 1.8V (±5%); each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 42 | VDD1P0 | power_in | 1.0V (+15.5%, -5%) core analog power supply; each pin requires 1µF and 0.1µF bypass capacitors to ground |
| 43 | RESET_N | input | Active-low hardware reset input; pulse width minimum 1µs at low level initializes and reinitializes DP83867; has internal pull-up resistor |
| 44 | INT/PWDN | bidirectional | Configurable as interrupt output or power-down input; default function is power-down (active-low); can be programmed via CFG3 register (address 0x001E) bit 7 as open-drain interrupt output |
| 45 | LED_2 | output | Configurable LED output for status indication; default function shows receive or transmit activity; alternate functions via LEDCR1 register (address 0x0018) bits 11:8; strap configuration pin for RGMII clock skew |
| 46 | LED_1 | output | Configurable LED output for status indication; default function indicates 1000BASE-T link established; alternate functions via LEDCR1 register (address 0x0018) bits 7:4 |
| 47 | LED_0 | output | Configurable LED output for status indication; default function indicates any speed link established; alternate functions via LEDCR1 register (address 0x0018) bits 3:0 |
| 48 | VDDA1P8 | power_in | 1.8V (±5%) analog power supply and die attach pad (GND); may be left floating in dual supply mode or connected to 1.8V source in triple supply mode with 1µF and 0.1µF bypass capacitors |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDA2P5 supply voltage absolute maximum | VDDA2P5 | -0.3 | 3 | V | 9 | ||
| VDDA1P8 supply voltage absolute maximum | VDDA1P8 | -0.3 | 2.1 | V | 9 | ||
| Core supply voltage absolute maximum (VDD1P1/VDD1P0) | VDD1P1/VDD1P0 | -0.3 | 1.3 | V | 9 | ||
| VDDIO absolute maximum, 3.3V option | VDDIO | -0.3 | 3.8 | V | 3.3V option | 9 | |
| VDDIO absolute maximum, 2.5V option | VDDIO | -0.3 | 3 | V | 2.5V option | 9 | |
| VDDIO absolute maximum, 1.8V option | VDDIO | -0.3 | 2.1 | V | 1.8V option | 9 | |
| MDI pins voltage absolute maximum | MDI | -0.3 | 6.5 | V | 9 | ||
| MAC interface, MDIO, MDC, GPIO voltage absolute maximum | -0.3 | V | max printed as VDDIO + 0.3 | 9 | |||
| INT/PWDN, RESET voltage absolute maximum | -0.3 | V | max printed as VDDIO + 0.3 | 9 | |||
| JTAG voltage absolute maximum | -0.3 | V | max printed as VDDIO + 0.3 | 9 | |||
| XI oscillator clock input voltage absolute maximum | XI | -0.3 | 2.1 | V | 9 | ||
| Storage temperature | Tstg | -60 | 150 | °C | 9 | ||
| VDDA2P5 supply voltage recommended | VDDA2P5 | 2.375 | 2.5 | 2.625 | V | 9 | |
| VDDA1P8 supply voltage recommended | VDDA1P8 | 1.71 | 1.8 | 1.89 | V | 9 | |
| VDD1P0 supply voltage recommended (RGZ) | VDD1P0 | 0.95 | 1 | 1.155 | V | RGZ package | 9 |
| VDDIO supply voltage recommended, 3.3V option | VDDIO | 3.15 | 3.3 | 3.45 | V | 3.3V option | 9 |
| VDDIO supply voltage recommended, 2.5V option | VDDIO | 2.375 | 2.5 | 2.625 | V | 2.5V option | 9 |
| VDDIO supply voltage recommended, 1.8V option | VDDIO | 1.71 | 1.8 | 1.89 | V | 1.8V option | 9 |
| Operating free-air temperature, industrial (DP83867IRRGZ) | -40 | 25 | 85 | °C | natural ventilation | 10 | |
| Operating junction temperature, industrial (DP83867IRRGZ) | -40 | 105 | °C | DP83867IRRGZ | 10 | ||
| High-level output voltage, 3.3V VDDIO | VOH | 2 | V | IOH = -4mA | 10 | ||
| Low-level output voltage, 3.3V VDDIO | VOL | 0.6 | V | IOL = 4mA | 10 | ||
| High-level input voltage, 3.3V VDDIO | VIH | 1.7 | V | 10 | |||
| Low-level input voltage, 3.3V VDDIO | VIL | 0.7 | V | 10 | |||
| Low-level output voltage, 2.5V VDDIO | VOL | 0.6 | V | IOL = 4mA | 10 | ||
| High-level input voltage, 2.5V VDDIO | VIH | 1.7 | V | 10 | |||
| Low-level input voltage, 2.5V VDDIO | VIL | 0.7 | V | 10 | |||
| Low-level output voltage, 1.8V VDDIO | VOL | 0.2 | V | IOL = 1mA | 10 | ||
| XI high-level input voltage | VIH | 1.4 | V | 10 | |||
| XI low-level input voltage | VIL | 0.45 | V | 10 | |||
| Input high current | IIH | -10 | 10 | µA | VIN = VDD, TA = -40°C to +85°C | 11 | |
| Input low current | IIL | -10 | 10 | µA | VIN = GND, TA = -40°C to +85°C | 11 | |
| Three-state output current | IOZ | -10 | 10 | µA | VOUT = VDD, VOUT = GND, TA = -40°C to +85°C | 11 | |
| SGMII PMD output differential peak voltage, 10BASE-Te (MDI IRRGZ) | VOD-10 | 1.54 | 1.75 | 1.96 | V | MDI IRPAP/IRRGZ, peak differential | 11 |
| SGMII PMD output differential peak voltage, 100BASE-TX (MDI IRRGZ) | VOD-100 | 0.95 | 1 | 1.05 | V | MDI IRPAP/IRRGZ, peak differential | 11 |
| SGMII PMD output differential peak voltage, 1000BASE-T (MDI IRRGZ) | VOD-1000 | 0.67 | 0.745 | 0.82 | V | MDI IRPAP/IRRGZ, peak differential | 11 |
| Junction-to-ambient thermal resistance (RGZ 48-pin) | RθJA | 30.8 | °C/W | RGZ (QFN) 48 pin | 10 | ||
| Junction-to-case (top) thermal resistance (RGZ 48-pin) | RθJC(top) | 18.7 | °C/W | RGZ (QFN) 48 pin | 10 | ||
| Junction-to-case (bottom) thermal resistance (RGZ 48-pin) | RθJC(bot) | 1.4 | °C/W | RGZ (QFN) 48 pin | 10 | ||
| Junction-to-board thermal resistance (RGZ 48-pin) | RθJB | 7.5 | °C/W | RGZ (QFN) 48 pin | 10 | ||
| Junction-to-top characterization parameter (RGZ 48-pin) | ψJT | 0.3 | °C/W | RGZ (QFN) 48 pin | 10 | ||
| Junction-to-board characterization parameter (RGZ 48-pin) | ψJB | 7.5 | °C/W | RGZ (QFN) 48 pin | 10 |
CAD (KiCad official)
- Symbol:
DP83867IRRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
dp83867irrgzr-etched.step/dp83867irrgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83867irrgzr.step/dp83867irrgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (136 pp, sha256
86c425421d9ee17a, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).