component
TL431LA
Public Made by Adomby adom
PJSEMI Voltage Reference, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTL431LA
PJSEMI · Voltage Reference · SOT-23
TL431LA from PJSEMI, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | input | Reference input that sets the cathode voltage through an external R1/R2 divider, with Vref of 2.5V (2.488V to 2.512V for the 0.5% TL431LA) and typical input current of 1 µA. |
| 2 | CATHODE | passive | Cathode (K) of the programmable shunt reference, regulating from VREF to 36V (37V absolute maximum) with cathode current of 0.5mA to 100mA. |
| 3 | ANODE | power_in | Anode (A) of the shunt reference, normally connected to the lowest potential (ground). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | SOT-23 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reference Input Voltage | VREF | 2.488 | 2.5 | 2.512 | V | VKA=VREF, IKA=10mA, Fig1 (TL431LA 0.5% row) | 5 |
| Deviation of Reference Input Voltage Over Temperature | ΔVREF | 16 | 25 | mV | VKA=VREF, IKA=10mA, TMIN ≤ TA ≤ TMAX, Fig1 | 5 | |
| Ratio of Change in Reference Input Voltage to Change in Cathode Voltage (10V to VREF) | ΔVREF/ΔVKA | -1 | -2.7 | mV/V | IKA=10mA, ΔVKA=10V~VREF, Fig2 | 5 | |
| Ratio of Change in Reference Input Voltage to Change in Cathode Voltage (36V to 10V) | ΔVREF/ΔVKA | -1 | -2 | mV/V | IKA=10mA, ΔVKA=36V~10V, Fig2 | 5 | |
| Reference Input Current | IREF | 1 | 2 | µA | IKA=10mA, R1=10KΩ, R2=∞, Fig2 | 5 | |
| Deviation of Reference Input Current Over Full Temperature Range | ΔIREF | 0.2 | 0.4 | µA | IKA=10mA, R1=10KΩ, R2=∞, TA=full Temperature, Fig2 | 5 | |
| Minimum Cathode Current for Regulation | IKA(MIN) | 50 | 85 | µA | VKA=VREF, Fig1 | 5 | |
| Off-State Cathode Current | IKA(OFF) | 0.05 | 0.5 | µA | VKA=36V, VREF=0, Fig3 | 5 | |
| Dynamic Impedance | ZKA | 0.2 | 0.5 | Ω | VKA=VREF, IKA=1~100mA, f≤1.0KHz | 5 | |
| Cathode Voltage (recommended maximum) | VKA | 36 | V | 4 | |||
| Cathode Current | IKA | 0.5 | 100 | mA | 4 | ||
| Cathode Voltage | VKA | 37 | V | 4 | |||
| Cathode Current Range (Continuous) | IKA | -100 | 150 | mA | Continuous | 4 | |
| Reference Input Current Range | IREF | -0.05 | 10 | mA | 4 | ||
| Operating Temperature | TOPR | -40 | 125 | °C | 4 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 4 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 416 | °C/W | SOT-23 package | 4 |
CAD (KiCad official)
- Symbol:
TL431LA - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
tl431la-etched.step/tl431la-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tl431la.step/tl431la.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PJSEMI datasheet (11 pp, sha256
856fea739613191f, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).