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XL4021B

Public Made by Adom

by adom

XINLUDA Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XL4021B

XINLUDA · Shift Registers · SOP-16

XL4021B from XINLUDA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PI-8 input Parallel data input for register stage 8, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
2 Q6 output Buffered output taken from register stage 6 of the 8-stage shift register.
3 Q8 output Buffered output of register stage 8, the final stage of the shift register.
4 PI-4 input Parallel data input for register stage 4, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
5 PI-3 input Parallel data input for register stage 3, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
6 PI-1 input Parallel data input for register stage 1, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
7 PI-2 input Parallel data input for register stage 2, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
8 VSS power_in Negative supply voltage; all voltages in the datasheet are referenced to this terminal.
9 PARALLEL/SERIAL CONTROL input Selects entry mode: low shifts serial data in on the positive clock edge, high jams the parallel inputs into the register.
10 CLOCK input Clock input; serial and parallel entry are synchronized to its positive transition, with recommended clock frequency up to 3 MHz at 5 V, 6 MHz at 10 V and 8.5 MHz at 15 V.
11 SERIAL IN input Serial data input, shifted into the register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low.
12 Q7 output Buffered output taken from register stage 7 of the 8-stage shift register.
13 PI-5 input Parallel data input for register stage 5, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
14 PI-6 input Parallel data input for register stage 6, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
15 PI-7 input Parallel data input for register stage 7, loaded when PARALLEL/SERIAL CONTROL is high; input voltage must stay within VSS-0.5 V to VDD+0.5 V and input current is limited to ±10 mA.
16 VDD power_in Positive supply voltage, recommended 3 V to 18 V with an absolute maximum of +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply-voltage range VDD 20 V Voltages referenced to VSS terminal 4
DC input current, any one input VO -10 10 mA 4
Power dissipation per package PD 500 mW For TA = -55°C to +100°C 4
Device dissipation per output transistor PDDO 100 mW For TA = full package-temperature range (all package types) 4
Operating temperature range TA -40 85 °C 4
Storage temperature range Tstg -50 125 °C 4
Lead temperature (during soldering) TL 265 °C At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10s max 4
Supply-voltage range VDD 3 18 V TA = Full Package-Temperature Range 4
Clock pulse width tw 180 ns VDD=5 V; TA=25°C unless otherwise specified 4
Clock pulse width tw 80 ns VDD=10 V; TA=25°C unless otherwise specified 4
Clock pulse width tw 50 ns VDD=15 V; TA=25°C unless otherwise specified 4
Clock frequency fCL 3 MHz VDD=5 V; TA=25°C unless otherwise specified 4
Clock frequency fCL 6 MHz VDD=10 V; TA=25°C unless otherwise specified 4
Clock frequency fCL 8.5 MHz VDD=15 V; TA=25°C unless otherwise specified 4
Clock rise and fall time trCL, tfCL 15 μs VDD=5 V; TA=25°C unless otherwise specified 4
Set-up time, serial input (ref. to CL) ts 120 ns VDD=5 V; TA=25°C unless otherwise specified 4
Set-up time, serial input (ref. to CL) ts 80 ns VDD=10 V; TA=25°C unless otherwise specified 4
Set-up time, serial input (ref. to CL) ts 60 ns VDD=15 V; TA=25°C unless otherwise specified 4
Set-up time, parallel inputs (ref. to P/S) ts 50 ns VDD=5 V; TA=25°C unless otherwise specified 4
Set-up time, parallel inputs (ref. to P/S) ts 30 ns VDD=10 V; TA=25°C unless otherwise specified 4
Set-up time, parallel inputs (ref. to P/S) ts 20 ns VDD=15 V; TA=25°C unless otherwise specified 4
Parallel/serial pulse width (XL4021B) tw 160 ns VDD=5 V; TA=25°C unless otherwise specified 4
Parallel/serial pulse width (XL4021B) tw 80 ns VDD=10 V; TA=25°C unless otherwise specified 4
Parallel/serial pulse width (XL4021B) tw 50 ns VDD=15 V; TA=25°C unless otherwise specified 4
Parallel/serial removal time (XL4021B) tREM 280 ns VDD=5 V; TA=25°C unless otherwise specified 4
Parallel/serial removal time (XL4021B) tREM 140 ns VDD=10 V; TA=25°C unless otherwise specified 4
Parallel/serial removal time (XL4021B) tREM 100 ns VDD=15 V; TA=25°C unless otherwise specified 4
Quiescent device current IQD 5 μA VIN=0 V, VDD=5 V, TA=+25°C 5
Quiescent device current IQD 10 μA VIN=0 V, VDD=10 V, TA=+25°C 5
Quiescent device current IQD 20 μA VIN=0 V, VDD=15 V, TA=+25°C 5
Quiescent device current IQD 100 μA VIN=0 V, VDD=20 V, TA=+25°C 5
Output low (sink) current IQL 0.51 mA VO=0.4 V, VIN=0 V, VDD=5 V, TA=+25°C 5
Output low (sink) current IQL 1.3 mA VO=0.5 V, VIN=0 V, VDD=10 V, TA=+25°C 5
Output low (sink) current IQL 3.4 mA VO=1.5 V, VIN=0 V, VDD=15 V, TA=+25°C 5
Output high (source) current IQH -0.51 mA VO=4.6 V, VIN=0 V, VDD=5 V, TA=+25°C 5
Output high (source) current IQH -1.6 mA VO=2.5 V, VIN=0 V, VDD=5 V, TA=+25°C 5
Output high (source) current IQH -1.3 mA VO=9.5 V, VIN=0 V, VDD=10 V, TA=+25°C 5
Output high (source) current IQH -3.4 mA VO=13.5 V, VIN=0 V, VDD=15 V, TA=+25°C 5
Output voltage low-level VOL 0.05 V VIN=0 V, VDD=5 V, TA=+25°C 5
Output voltage high-level VOH 4.95 V VIN=0 V, VDD=5 V, TA=+25°C 5
Output voltage high-level VOH 9.95 V VIN=0 V, VDD=10 V, TA=+25°C 5
Output voltage high-level VOH 14.95 V VIN=0 V, VDD=15 V, TA=+25°C 5
Input low voltage VIL 1.5 V VO=0.5 V, 4.5 V; VDD=5 V 5
Input low voltage VIL 3 V VO=1 V, 9 V; VDD=10 V 5
Input low voltage VIL 4 V VO=1.5 V, 13.5 V; VDD=15 V 5
Input high voltage VIH 3.5 V VO=0.5 V, 4.5 V; VDD=5 V 5
Input high voltage VIH 7 V VO=1 V, 9 V; VDD=10 V 5
Input high voltage VIH 11 V VO=1.5 V, 13.5 V; VDD=15 V 5
Input current IIN 1 μA VIN=0 V, VDD=18 V 5
Propagation delay time tPLH, tPHL 320 ns VDD=5 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Propagation delay time tPLH, tPHL 160 ns VDD=10 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Propagation delay time tPLH, tPHL 120 ns VDD=15 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Transition time tTHL, tTLH 200 ns VDD=5 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Transition time tTHL, tTLH 100 ns VDD=10 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Transition time tTHL, tTLH 80 ns VDD=15 V; TA=25°C, tr,tf=20 ns, CL=50 pF, RL=200 KΩ 7
Average input capacitance CI 7.5 pF Any input 7

CAD (KiCad official)

  • Symbol: XL4021B
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: xl4021b-etched.step / xl4021b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl4021b.step / xl4021b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (10 pp, sha256 1c36cab23d66cacb, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF