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LTP7693XF20
Public Made by Adomby adom
Linearin(先积集成) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTP7693XF20
Linearin(先积集成) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(3.5x3.5)
LTP7693XF20 from Linearin(先积集成), in a QFN-20(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a 47 µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. |
| 2 | SNS | input | Output voltage sense input connected to the internal R1 resistor; connect it to the load side of the output trace only if the ANY-OUT feature is used, otherwise leave it floating. |
| 3 | FB | input | Feedback pin connected to the error amplifier; a 10 nF feed-forward capacitor from FB to OUT placed as close to the device as possible is recommended, and it can disrupt PG functionality. |
| 4 | PG | output | Active-high power-good pin implemented as an open-drain output that indicates when the output voltage reaches VIT(PG) of the target. |
| 5 | 50 mV | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating; connecting to ground increases the output voltage while connecting to SNS increases ANY-OUT resolution but decreases its range. |
| 6 | 100 mV | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating when not in use. |
| 7 | 200 mV | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating when not in use. |
| 8 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
| 9 | 400 mV | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating when not in use. |
| 10 | 800 mV | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating when not in use. |
| 11 | 1.6 V | input | ANY-OUT voltage setting pin that should be connected to ground, connected to SNS, or left floating when not in use. |
| 12 | BIAS | power_in | BIAS supply voltage that enables low-input, low-output (LILO) operation and improves dc and ac performance for VIN ≤ 2.2 V; a 10 µF or larger capacitor must be connected from this pin to ground, and if unused it must be floating or tied to ground. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin where an external capacitor to ground reduces reference noise and enables soft-start; a 10 nF or larger capacitor placed close to the pin is recommended. |
| 14 | EN | input | Enable pin where logic high enables the device and logic low disables it; if enable is not required it must be connected to IN, and when a BIAS supply is used VEN must be high only after VIN is established. |
| 15 | IN | power_in | Input supply voltage pin; a 47 µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to ground is recommended and should be placed as close to the input as possible. |
| 16 | IN | power_in | Input supply voltage pin; a 47 µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to ground is recommended and should be placed as close to the input as possible. |
| 17 | IN | power_in | Input supply voltage pin; a 47 µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to ground is recommended and should be placed as close to the input as possible. |
| 18 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
| 19 | OUT | power_out | Regulated output pin; a 47 µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. |
| 20 | OUT | power_out | Regulated output pin; a 47 µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. |
| 21 | Thermal pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin(先积集成) |
| Package | QFN-20(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN, BIAS, PG, EN voltage | -0.3 | 7 | V | 8 | |||
| IN, BIAS, PG, EN voltage (5% duty cycle) | -0.3 | 7.5 | V | 5% duty cycle, pulse duration = 200 µs | 8 | ||
| NR/SS, FB voltage | -0.3 | 3.6 | V | 8 | |||
| PG current (sink current into device) | 5 | mA | 8 | ||||
| Maximum junction temperature | TJ | -55 | 150 | °C | 8 | ||
| Storage temperature | TSTG | -55 | 150 | °C | 8 | ||
| ESD Human Body Model | ESD | -2000 | 2000 | V | Human Body Model | 8 | |
| ESD Charged-device model | -500 | 500 | V | Charged-device model | 8 | ||
| Input supply voltage range | VIN | 1.1 | 6.5 | V | 9 | ||
| Bias supply voltage range | VBIAS | 3 | 6.5 | V | 9 | ||
| Output voltage range | VOUT | 0.8 | 5.15 | V | 9 | ||
| Enable voltage range | VEN | 0 | V | 9 | |||
| Output current | IOUT | 0 | 3 | A | 9 | ||
| Input capacitor | CIN | 10 | μF | 9 | |||
| Output capacitor | COUT | 47 | μF | 9 | |||
| Power-good pullup resistance | RPG | 10 | 100 | kΩ | 9 | ||
| NR/SS capacitor | CNR/SS | 10 | nF | 9 | |||
| Top resistor value in feedback network for adjustable operation | R1 | 6.05 | kΩ | 9 | |||
| Bottom resistor value in feedback network for adjustable operation | R2 | 160 | kΩ | 9 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 9 | ||
| Input supply UVLO with BIAS (rising) | VUVLO1(IN) | 1 | 1.085 | V | VIN rising with VBIAS = 3.0 V | 10 | |
| Input supply UVLO without BIAS (rising) | VUVLO2(IN) | 1.31 | 1.39 | V | VIN rising | 10 | |
| Bias supply UVLO (rising) | VUVLO(BIAS) | 2.89 | 3 | V | VBIAS rising, VIN = 1.1 V | 10 | |
| EN pin input current | IEN | -0.1 | 0.1 | μA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 10 | |
| BIAS pin current | IBIAS | 2.4 | 3.5 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT(nom) = 0.8 V, IOUT = 3 A | 10 | |
| EN pin low-level input voltage (disable device) | VIL(EN) | 0 | 0.5 | V | 10 | ||
| EN pin high-level input voltage (enable device) | VIH(EN) | 1.1 | 6.5 | V | 10 | ||
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 10 | ||
| PG pin leakage current | Ilkg(PG) | 1 | μA | VOUT > VIT(PG), VPG = 6.5 V | 10 | ||
| NR/SS pin charging current | INR/SS | 2 | 6.6 | 9 | μA | VNR/SS = GND, VIN = 6.5 V | 10 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 10 | |
| Input voltage operation range | VIN | 1.1 | 6.5 | V | 11 | ||
| Bias supply voltage range | VBIAS | 3 | 6.5 | V | VIN = 1.1 V | 11 | |
| Output voltage accuracy | -1 | 1 | % | 0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 11 | ||
| Output voltage accuracy with BIAS | -0.75 | 0.75 | % | VIN = 1.1 V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 11 | ||
| Dropout voltage (VOUT = 1.1 V) | VDO | 140 | 250 | mV | VOUT = 1.1 V, IOUT = 3 A | 11 | |
| Dropout voltage (VOUT = 3.3 V) | VDO | 170 | 300 | mV | VOUT = 3.3 V, IOUT = 3 A | 11 | |
| Dropout voltage (VOUT = 5 V) | VDO | 200 | 340 | mV | VOUT = 5 V, IOUT = 3 A | 11 | |
| Output current limit | ILIM | 4.2 | 5.2 | A | VOUT = 90%VOUT-NOM, VIN = VOUT(nom) + 0.4 V | 11 | |
| GND pin current (VIN = 6.5 V) | IGND | 3 | 4 | mA | VIN = 6.5 V, IOUT = 5 mA | 11 | |
| GND pin current (VIN = 1.4 V) | IGND | 4.3 | 5.5 | mA | VIN = 1.4 V, IOUT = 3 A | 11 | |
| GND pin current in shutdown | IGND | 1.2 | 25 | μA | Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V | 11 | |
| PG pin threshold (falling VOUT) | VIT(PG) | 82 | 88 | 93 | %VOUT | For falling VOUT | 12 |
CAD (KiCad official)
- Symbol:
LTP7693XF20 - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: QFN-20(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ltp7693xf20-etched.step/ltp7693xf20-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltp7693xf20.step/ltp7693xf20.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Linearin(先积集成) datasheet (32 pp, sha256
7a409ca103c801aa, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).