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sn74lv164adr

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by Ray

Texas Instruments Shifting Register, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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SN74LV164ADR

Texas Instruments · Shifting Register · SOIC-14

SN74LV164ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Serial input A. Data is AND-ed with input B and clocked into stage QA on the rising edge of CLK. High-level input voltage VIH = VCC × 0.7 (3 V ≤ VCC ≤ 5.5 V).
2 B input Serial input B. Data is AND-ed with input A and clocked into stage QA on the rising edge of CLK. Tie high if unused so input A alone drives the shift register.
3 QA output Parallel output A - first stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
4 QB output Parallel output B - second stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
5 QC output Parallel output C - third stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
6 QD output Parallel output D - fourth stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
7 GND power_in Ground reference (0 V). Return for logic and output drive current; keep to a low-impedance plane to limit ground bounce (typical VOLP < 0.8 V at VCC = 3.3 V).
8 CLK input Storage/shift clock. Data at inputs A and B are transferred one stage on each rising edge. Minimum high/low pulse width 5 ns at VCC = 3.3 V.
9 CLR input Asynchronous active-low clear. Driving CLR low forces all QA-QH outputs low independent of CLK. Minimum low pulse width 5 ns at VCC = 3.3 V; tie high for normal shift operation.
10 QE output Parallel output E - fifth stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
11 QF output Parallel output F - sixth stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
12 QG output Parallel output G - seventh stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
13 QH output Parallel output H - eighth (final) stage of the 8-bit shift register. Drives ±6 mA at VCC = 3.3 V, ±12 mA at VCC = 5 V.
14 VCC power_in Supply voltage, 2 V to 5.5 V (absolute maximum 7 V). ICC ≤ 20 µA at VCC = 5.5 V. Bypass locally with a 0.1 µF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

  • SN74LV164ADRD
  • SN74LV164ADR
  • SN74LV164ADRDB
  • SN74LV164ADRDBR
  • SN74LV164ADRDGV
  • SN74LV164ADRDGVR
  • SN74LV164ADRNS
  • SN74LV164ADRNSR
  • SN74LV164ADRPW
  • SN74LV164ADRPWR
  • SN74LV164ADRRGY
  • SN74LV164ADRRGYR
  • SN74LV164ADRBQA
  • SN74LV164ADRBQAR

CAD (KiCad official)

  • Symbol: SN74LV164ADR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 6789cef5ba0c0c25, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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PCB Footprint

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Datasheet

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