component
MC74HCT595ADG
Public Made by Adomby adom
onsemi Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HCT595ADG
onsemi · Registers · SOIC-16
MC74HCT595ADG from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, three-state parallel latch output B; forced to high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, three-state parallel latch output C; forced to high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, three-state parallel latch output D; forced to high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, three-state parallel latch output E; forced to high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, three-state parallel latch output F; forced to high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, three-state parallel latch output G; forced to high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, three-state parallel latch output H; forced to high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground reference pin; all voltages are referenced to GND, and VCC must be held between 4.5 and 5.5 V relative to it. |
| 9 | SQH | output | Noninverted serial data output from the eighth shift register stage; it does not have three-state capability. |
| 10 | RESET | input | Active-low asynchronous reset for the shift register only; a low resets the shift register and does not affect the 8-bit latch. |
| 11 | SHIFT CLOCK | input | Shift register clock; a low-to-high transition shifts the data at the serial input A into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock; a low-to-high transition latches the shift register data into the 8-bit latch. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; a low lets the latch data appear on QA-QH, while a high forces QA-QH into high impedance without affecting SQH. |
| 14 | A | input | Serial data input shifted into the 8-bit shift register on each low-to-high shift clock transition. |
| 15 | QA | tri_state | Noninverted, three-state parallel latch output A; forced to high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply pin; the recommended DC supply range is 4.5 to 5.5 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.8 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Output Voltage, QA−QH | VOH | 4.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Output Voltage, QA−QH (125°C column) | VOH | 3.7 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; 125°C | 4 | ||
| Maximum Low-Level Output Voltage, QA−QH | VOL | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Output Voltage, QA−QH (125°C column) | VOL | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; 125°C | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 4.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Output Voltage, SQH (125°C column) | VOH | 3.7 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125°C | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Output Voltage, SQH (125°C column) | VOL | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125°C | 4 | ||
| Maximum Input Leakage Current (125°C column) | Iin | -1 | 1 | µA | VCC 5.5 V; Vin = VCC or GND; 125°C | 4 | |
| Maximum Three-State Leakage Current, QA−QH (125°C column) | IOZ | -10 | 10 | µA | VCC 5.5 V; output high-impedance; Vin = VIL or VIH; Vout = VCC or GND; 125°C | 4 | |
| Maximum Quiescent Supply Current (per package, 125°C column) | ICC | 160 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0 A; 125°C | 4 | ||
| Additional Quiescent Supply Current (≥ −55°C) | ICC | 2.9 | mA | VCC 5.5 V; Vin = 2.4 V on any one input; Vin = VCC or GND on other inputs; Iout = 0 A; ≥ −55°C | 4 | ||
| Additional Quiescent Supply Current (25 to 125°C) | ICC | 2.4 | mA | VCC 5.5 V; Vin = 2.4 V on any one input; Vin = VCC or GND on other inputs; Iout = 0 A; 25 to 125°C | 4 | ||
| Maximum Clock Frequency (50% duty cycle, 125°C column) | fmax | 20 | MHz | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH (125°C column) | tPLH, tPHL | 42 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Propagation Delay, Reset to SQH (125°C column) | tPHL | 44 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA−QH (125°C column) | tPLH, tPHL | 42 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Propagation Delay, Output Enable to QA−QH, high-impedance (125°C column) | tPLZ, tPHZ | 45 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Propagation Delay, Output Enable to QA−QH, enable (125°C column) | tPZL, tPZH | 41 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Output Transition Time, QA−QH (125°C column) | tTLH, tTHL | 18 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Output Transition Time, SQH (125°C column) | tTLH, tTHL | 22 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 5 | |||
| Maximum Three-State Output Capacitance (output high-impedance), QA−QH | Cout | 15 | pF | Output in high-impedance state, QA−QH | 5 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock (125°C column) | tsu | 15 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Minimum Setup Time, Shift Clock to Latch Clock (125°C column) | tsu | 22 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Minimum Hold Time, Shift Clock to Serial Data Input A | th | 5 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns | 5 | ||
| Minimum Recovery Time, Reset Inactive to Shift Clock (125°C column) | trec | 15 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Minimum Pulse Width, Reset (125°C column) | tw | 18 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Minimum Pulse Width, Shift Clock (125°C column) | tw | 15 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Minimum Pulse Width, Latch Clock (125°C column) | tw | 15 | ns | VCC 4.5 to 5.5 V; tr = tf = 6.0 ns; 125°C | 5 | ||
| Maximum Input Rise and Fall Times | tr, tf | 500 | ns | VCC 4.5 to 5.5 V; Figure 1 | 5 | ||
| DC Supply Voltage (Referenced to GND), recommended | VCC | 4.5 | 5.5 | V | Referenced to GND | 3 | |
| DC Input Voltage, Output Voltage (Referenced to GND), recommended | Vin, Vout | 0 | V | Referenced to GND; printed maximum is VCC | 3 | ||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 3 | ||
| Input Rise/Fall Time, recommended | tr, tf | 0 | 500 | ns | Figure 1 | 3 | |
| DC Supply Voltage (Referenced to GND), absolute maximum | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage (Referenced to GND), absolute maximum | Vin | -0.5 | V | Referenced to GND; printed maximum is VCC + 0.5 | 3 | ||
| DC Output Voltage (Referenced to GND), absolute maximum | Vout | -0.5 | V | Referenced to GND; printed maximum is VCC + 0.5 | 3 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin | 3 | |
| DC Output Current, per Pin | Iout | -35 | 35 | mA | Per pin | 3 | |
| DC Supply Current, VCC and GND Pins | ICC | -75 | 75 | mA | VCC and GND pins | 3 | |
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Still air, SOIC package; derate −7 mW/°C from 65 to 125°C | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP) | TL | 260 | °C | 1 mm from case for 10 seconds | 3 |
CAD (KiCad official)
- Symbol:
MC74HCT595ADG - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hct595adg-etched.step/mc74hct595adg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct595adg.step/mc74hct595adg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (12 pp, sha256
a09e1caabec3fe23, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).