component
XD74LS02
Public Made by Adomby adom
XINLUDA Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD74LS02
XINLUDA · Gates · DIP-14
XD74LS02 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Gate 1 output, driving up to 8 mA IOL (VOL max 0.5 V) and -400 µA IOH (VOH min 2.7 V). |
| 2 | 1A | input | Gate 1 input A, with VIH min 2.0 V and VIL max 0.8 V. |
| 3 | 1B | input | Gate 1 input B, with VIH min 2.0 V and VIL max 0.8 V. |
| 4 | 2Y | output | Gate 2 output, driving up to 8 mA IOL (VOL max 0.5 V) and -400 µA IOH (VOH min 2.7 V). |
| 5 | 2A | input | Gate 2 input A, with VIH min 2.0 V and VIL max 0.8 V. |
| 6 | 2B | input | Gate 2 input B, with VIH min 2.0 V and VIL max 0.8 V. |
| 7 | GND | power_in | Ground, 0 V reference for the device. |
| 8 | 3A | input | Gate 3 input A, with VIH min 2.0 V and VIL max 0.8 V. |
| 9 | 3B | input | Gate 3 input B, with VIH min 2.0 V and VIL max 0.8 V. |
| 10 | 3Y | output | Gate 3 output, driving up to 8 mA IOL (VOL max 0.5 V) and -400 µA IOH (VOH min 2.7 V). |
| 11 | 4A | input | Gate 4 input A, with VIH min 2.0 V and VIL max 0.8 V. |
| 12 | 4B | input | Gate 4 input B, with VIH min 2.0 V and VIL max 0.8 V. |
| 13 | 4Y | output | Gate 4 output, driving up to 8 mA IOL (VOL max 0.5 V) and -400 µA IOH (VOH min 2.7 V). |
| 14 | VCC | power_in | Positive supply, recommended 4.75 V to 5.25 V (typ 5.00 V), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 3 | |
| High-level output current | IOH | -400 | A | 3 | |||
| Low-level output current | IOL | 8 | mA | 3 | |||
| Operating temperature | Topr | 0 | 25 | 70 | C | 3 | |
| Supply voltage | VCC | 7 | V | 3 | |||
| Input voltage | VIN | 7 | V | 3 | |||
| Power dissipation | PT | 400 | mW | 3 | |||
| Storage temperature | Tstg | -50 | 150 | C | 3 | ||
| ESD HBM | V(ESD) | 2000 | V | Human body model, all pins | 3 | ||
| ESD CDM | V(ESD) | 200 | V | Charged device model, all pins | 3 | ||
| High-level input voltage | VIH | 2 | V | TA = 0 C to 70 C | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | TA = 0 C to 70 C | 4 | ||
| High-level output voltage | VOH | 2.7 | V | VCC = 4.75 V, VIL= 0.8 V, IOH = -400 A | 4 | ||
| Low-level output voltage | VOL | 0.5 | V | IOL = 8 mA | 4 | ||
| Low-level output voltage | VOL | 0.4 | V | VCC = 4.75 V, VIH = 2 V, IOL = 4 mA | 4 | ||
| High-level input current | IIH | 20 | A | VCC = 5.25 V, VI = 2.7 V | 4 | ||
| Low-level input current | IIL | -0.4 | mA | VCC = 5.25 V, VI = 0.4 V | 4 | ||
| Input current at max input voltage | II | 0.1 | mA | VCC = 5.25 V, VI = 7 V | 4 | ||
| Short-circuit output current | IOS | -20 | -100 | mA | VCC = 5.25 V | 4 | |
| Supply current, outputs high | ICCH | 1.8 | 5.5 | mA | VCC = 5.25 V | 4 | |
| Supply current, outputs low | ICCL | 3.1 | 7 | mA | VCC = 5.25 V | 4 | |
| Input clamp voltage | VIK | -1.5 | V | VCC = 4.75 V, IIN = -18mA | 4 | ||
| Propagation delay time, low-to-high | tPLH | 12 | 20 | ns | VCC = 5V, TA=25 C, CL = 15 pF, RL = 2 k | 4 | |
| Propagation delay time, high-to-low | tPHL | 12 | 20 | ns | VCC = 5V, TA=25 C, CL = 15 pF, RL = 2 k | 4 |
CAD (KiCad official)
- Symbol:
XD74LS02 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls02-etched.step/xd74ls02-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls02.step/xd74ls02.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (6 pp, sha256
baf1fb5d0728c051, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).