component
SN74LVC126AQDRQ1
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LVC126AQDRQ1
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-14
SN74LVC126AQDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable for gate 1; when low, output 1Y is disabled and goes to high impedance. |
| 2 | 1A | input | Gate 1 input, which accepts 0 V to 5.5 V per the recommended operating conditions. |
| 3 | 1Y | tri_state | Gate 1 three-state output, which is high impedance when 1OE is low. |
| 4 | 2OE | input | Output enable for gate 2; when low, output 2Y is disabled and goes to high impedance. |
| 5 | 2A | input | Gate 2 input, which accepts 0 V to 5.5 V per the recommended operating conditions. |
| 6 | 2Y | tri_state | Gate 2 three-state output, which is high impedance when 2OE is low. |
| 7 | GND | power_in | Ground pin; the datasheet requires GND as the device reference. |
| 8 | 3Y | tri_state | Gate 3 three-state output, which is high impedance when 3OE is low. |
| 9 | 3A | input | Gate 3 input, which accepts 0 V to 5.5 V per the recommended operating conditions. |
| 10 | 3OE | input | Output enable for gate 3; when low, output 3Y is disabled and goes to high impedance. |
| 11 | 4Y | tri_state | Gate 4 three-state output, which is high impedance when 4OE is low. |
| 12 | 4A | input | Gate 4 input, which accepts 0 V to 5.5 V per the recommended operating conditions. |
| 13 | 4OE | input | Output enable for gate 4; when low, output 4Y is disabled and goes to high impedance. |
| 14 | VCC | power_in | Supply pin; the datasheet specifies an operating range of 1.65 V to 3.6 V and requires a bypass capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LVC126AQDRQ1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc126aqdrq1-etched.step/sn74lvc126aqdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc126aqdrq1.step/sn74lvc126aqdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
eeb9f93c78359a57, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).