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STM32L151VDT7X
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L151VDT7X
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32L151VDT7X from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant (FT) I/O; reset function PE2; alternate functions TIM3_ETR, LCD_SEG38, TRACECLK. |
| 2 | PE3 | bidirectional | 5 V tolerant (FT) I/O; reset function PE3; alternate functions TIM3_CH1, LCD_SEG39, TRACED0. |
| 3 | PE4 | bidirectional | 5 V tolerant (FT) I/O; reset function PE4; alternate functions TIM3_CH2, TRACED1. |
| 4 | PE5 | bidirectional | 5 V tolerant (FT) I/O; reset function PE5; alternate functions TIM9_CH1, TRACED2. |
| 5 | PE6-WKUP3 | bidirectional | 5 V tolerant (FT) I/O; reset function PE6; alternate functions TIM9_CH2, TRACED3; additional function WKUP3/RTC_TAMP3. |
| 6 | VLCD | power_in | LCD power supply pin; applicable to STM32L152xD-X devices only, and on STM32L151xD-X devices this pin must be connected to VDD. |
| 7 | PC13-WKUP2 | bidirectional | 5 V tolerant (FT) I/O; reset function PC13; additional functions WKUP2/RTC_TAMP1/RTC_TS/RTC_OUT. |
| 8 | PC14-OSC32_IN | bidirectional | Standard 3.3 V (TC) I/O; acts as OSC32_IN only when the LSE oscillator is on (LSEON), otherwise it is GPIO PC14. |
| 9 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V (TC) I/O; acts as OSC32_OUT only when the LSE oscillator is on (LSEON), otherwise it is GPIO PC15. |
| 10 | VSS_5 | power_in | Ground pin of the digital domain. |
| 11 | VDD_5 | power_in | Digital supply pin; device supply range is 1.65 V to 3.6 V per the feature list. |
| 12 | PH0-OSC_IN | bidirectional | Standard 3.3 V (TC) I/O; acts as OSC_IN only when the HSE oscillator is on (HSEON), otherwise it is GPIO PH0. |
| 13 | PH1-OSC_OUT | bidirectional | Standard 3.3 V (TC) I/O; acts as OSC_OUT only when the HSE oscillator is on (HSEON), otherwise it is GPIO PH1. |
| 14 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 15 | PC0 | bidirectional | 5 V tolerant (FT) I/O; reset function PC0; alternate functions LCD_SEG18, ADC_IN10, COMP1_INP. |
| 16 | PC1 | bidirectional | 5 V tolerant (FT) I/O; reset function PC1; alternate functions LCD_SEG19, ADC_IN11, COMP1_INP. |
| 17 | PC2 | bidirectional | 5 V tolerant (FT) I/O; reset function PC2; alternate functions LCD_SEG20, ADC_IN12, COMP1_INP. |
| 18 | PC3 | bidirectional | Standard 3.3 V (TC) I/O; reset function PC3; alternate functions LCD_SEG21, ADC_IN13, COMP1_INP. |
| 19 | VSSA | power_in | Ground pin for the analog domain (ADC, DAC, comparators). |
| 20 | VREF- | power_in | Negative reference voltage for the ADC; VSSA or VREF- must be tied to ground. |
| 21 | VREF+ | power_in | Positive reference voltage for the ADC; ranges from 1.8 V to VDDA and can be grounded if neither the ADC nor the DAC is used. |
| 22 | VDDA | power_in | Analog supply pin; ADC characteristics specify VDDA from 1.8 V to 3.6 V. |
| 23 | PA0-WKUP1 | bidirectional | 5 V tolerant (FT) I/O; reset function PA0; alternate functions TIM2_CH1_ETR, TIM5_CH1, USART2_CTS; additional function WKUP1/RTC_TAMP2/ADC_IN0/COMP1_INP. |
| 24 | PA1 | bidirectional | 5 V tolerant (FT) I/O; reset function PA1; alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS, LCD_SEG0; additional functions ADC_IN1, COMP1_INP, OPAMP1_VINP. |
| 25 | PA2 | bidirectional | 5 V tolerant (FT) I/O; reset function PA2; alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, LCD_SEG1; additional functions ADC_IN2, COMP1_INP, OPAMP1_VINM. |
| 26 | PA3 | bidirectional | Standard 3.3 V (TC) I/O; reset function PA3; alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, LCD_SEG2; additional functions ADC_IN3, COMP1_INP, OPAMP1_VOUT. |
| 27 | VSS_4 | power_in | Ground pin of the digital domain. |
| 28 | VDD_4 | power_in | Digital supply pin; device supply range is 1.65 V to 3.6 V per the feature list. |
| 29 | PA4 | bidirectional | Standard 3.3 V (TC) I/O; reset function PA4; alternate functions SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK; additional functions ADC_IN4, DAC_OUT1, COMP1_INP. |
| 30 | PA5 | bidirectional | Standard 3.3 V (TC) I/O; reset function PA5; alternate functions TIM2_CH1_ETR, SPI1_SCK; additional functions ADC_IN5, DAC_OUT2, COMP1_INP. |
| 31 | PA6 | bidirectional | 5 V tolerant (FT) I/O; reset function PA6; alternate functions TIM3_CH1, TIM10_CH1, SPI1_MISO, LCD_SEG3; additional functions ADC_IN6, COMP1_INP, OPAMP2_VINP. |
| 32 | PA7 | bidirectional | 5 V tolerant (FT) I/O; reset function PA7; alternate functions TIM3_CH2, TIM11_CH1, SPI1_MOSI, LCD_SEG4; additional functions ADC_IN7, COMP1_INP, OPAMP2_VINM. |
| 33 | PC4 | bidirectional | 5 V tolerant (FT) I/O; reset function PC4; alternate function LCD_SEG22; additional functions ADC_IN14, COMP1_INP. |
| 34 | PC5 | bidirectional | 5 V tolerant (FT) I/O; reset function PC5; alternate function LCD_SEG23; additional functions ADC_IN15, COMP1_INP. |
| 35 | PB0 | bidirectional | Standard 3.3 V (TC) I/O; reset function PB0; alternate functions TIM3_CH3, LCD_SEG5; additional functions ADC_IN8, COMP1_INP, OPAMP2_VOUT, VREF_OUT. |
| 36 | PB1 | bidirectional | 5 V tolerant (FT) I/O; reset function PB1; alternate functions TIM3_CH4, LCD_SEG6; additional functions ADC_IN9, COMP1_INP, VREF_OUT. |
| 37 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O; reset function BOOT1; additional function ADC_IN0b. |
| 38 | PE7 | bidirectional | Standard 3.3 V (TC) I/O; reset function PE7; additional functions ADC_IN22, COMP1_INP. |
| 39 | PE8 | bidirectional | Standard 3.3 V (TC) I/O; reset function PE8; additional functions ADC_IN23, COMP1_INP. |
| 40 | PE9 | bidirectional | Standard 3.3 V (TC) I/O; reset function PE9; alternate function TIM2_CH1_ETR; additional functions ADC_IN24, COMP1_INP. |
| 41 | PE10 | bidirectional | Standard 3.3 V (TC) I/O; reset function PE10; alternate function TIM2_CH2; additional functions ADC_IN25, COMP1_INP. |
| 42 | PE11 | bidirectional | 5 V tolerant (FT) I/O; reset function PE11; alternate function TIM2_CH3. |
| 43 | PE12 | bidirectional | 5 V tolerant (FT) I/O; reset function PE12; alternate functions TIM2_CH4, SPI1_NSS. |
| 44 | PE13 | bidirectional | 5 V tolerant (FT) I/O; reset function PE13; alternate function SPI1_SCK. |
| 45 | PE14 | bidirectional | 5 V tolerant (FT) I/O; reset function PE14; alternate function SPI1_MISO. |
| 46 | PE15 | bidirectional | 5 V tolerant (FT) I/O; reset function PE15; alternate function SPI1_MOSI. |
| 47 | PB10 | bidirectional | 5 V tolerant (FT) I/O; reset function PB10; alternate functions TIM2_CH3, I2C2_SCL, USART3_TX, LCD_SEG10. |
| 48 | PB11 | bidirectional | 5 V tolerant (FT) I/O; reset function PB11; alternate functions TIM2_CH4, I2C2_SDA, USART3_RX, LCD_SEG11. |
| 49 | VSS_1 | power_in | Ground pin of the digital domain. |
| 50 | VDD_1 | power_in | Digital supply pin; device supply range is 1.65 V to 3.6 V per the feature list. |
| 51 | PB12 | bidirectional | 5 V tolerant (FT) I/O; reset function PB12; alternate functions TIM10_CH1, I2C2_SMBA, SPI2_NSS, I2S2_WS, USART3_CK, LCD_SEG12; additional functions ADC_IN18, COMP1_INP. |
| 52 | PB13 | bidirectional | 5 V tolerant (FT) I/O; reset function PB13; alternate functions TIM9_CH1, SPI2_SCK, I2S2_CK, USART3_CTS, LCD_SEG13; additional functions ADC_IN19, COMP1_INP. |
| 53 | PB14 | bidirectional | 5 V tolerant (FT) I/O; reset function PB14; alternate functions TIM9_CH2, SPI2_MISO, USART3_RTS, LCD_SEG14; additional functions ADC_IN20, COMP1_INP. |
| 54 | PB15 | bidirectional | 5 V tolerant (FT) I/O; reset function PB15; alternate functions TIM11_CH1, SPI2_MOSI, I2S2_SD, LCD_SEG15; additional functions ADC_IN21, COMP1_INP, RTC_REFIN. |
| 55 | PD8 | bidirectional | 5 V tolerant (FT) I/O; reset function PD8; alternate functions USART3_TX, LCD_SEG28. |
| 56 | PD9 | bidirectional | 5 V tolerant (FT) I/O; reset function PD9; alternate functions USART3_RX, LCD_SEG29. |
| 57 | PD10 | bidirectional | 5 V tolerant (FT) I/O; reset function PD10; alternate functions USART3_CK, LCD_SEG30. |
| 58 | PD11 | bidirectional | 5 V tolerant (FT) I/O; reset function PD11; alternate functions USART3_CTS, LCD_SEG31. |
| 59 | PD12 | bidirectional | 5 V tolerant (FT) I/O; reset function PD12; alternate functions TIM4_CH1, USART3_RTS, LCD_SEG32. |
| 60 | PD13 | bidirectional | 5 V tolerant (FT) I/O; reset function PD13; alternate functions TIM4_CH2, LCD_SEG33. |
| 61 | PD14 | bidirectional | 5 V tolerant (FT) I/O; reset function PD14; alternate functions TIM4_CH3, LCD_SEG34. |
| 62 | PD15 | bidirectional | 5 V tolerant (FT) I/O; reset function PD15; alternate functions TIM4_CH4, LCD_SEG35. |
| 63 | PC6 | bidirectional | 5 V tolerant (FT) I/O; reset function PC6; alternate functions TIM3_CH1, I2S2_MCK, LCD_SEG24. |
| 64 | PC7 | bidirectional | 5 V tolerant (FT) I/O; reset function PC7; alternate functions TIM3_CH2, I2S3_MCK, LCD_SEG25. |
| 65 | PC8 | bidirectional | 5 V tolerant (FT) I/O; reset function PC8; alternate functions TIM3_CH3, LCD_SEG26. |
| 66 | PC9 | bidirectional | 5 V tolerant (FT) I/O; reset function PC9; alternate functions TIM3_CH4, LCD_SEG27. |
| 67 | PA8 | bidirectional | 5 V tolerant (FT) I/O; reset function PA8; alternate functions USART1_CK, MCO, LCD_COM0. |
| 68 | PA9 | bidirectional | 5 V tolerant (FT) I/O; reset function PA9; alternate functions USART1_TX, LCD_COM1. |
| 69 | PA10 | bidirectional | 5 V tolerant (FT) I/O; reset function PA10; alternate functions USART1_RX, LCD_COM2. |
| 70 | PA11 | bidirectional | 5 V tolerant (FT) I/O; reset function PA11; alternate functions USART1_CTS, SPI1_MISO; additional function USB_DM. |
| 71 | PA12 | bidirectional | 5 V tolerant (FT) I/O; reset function PA12; alternate functions USART1_RTS, SPI1_MOSI; additional function USB_DP. |
| 72 | PA13 | bidirectional | 5 V tolerant (FT) I/O; reset function JTMS-SWDIO (serial wire debug data). |
| 73 | PH2 | bidirectional | 5 V tolerant (FT) I/O; reset function PH2; no alternate function listed for this pin. |
| 74 | VSS_2 | power_in | Ground pin of the digital domain. |
| 75 | VDD_2 | power_in | Digital supply pin; device supply range is 1.65 V to 3.6 V per the feature list. |
| 76 | PA14 | bidirectional | 5 V tolerant (FT) I/O; reset function JTCK-SWCLK (serial wire debug clock). |
| 77 | PA15 | bidirectional | 5 V tolerant (FT) I/O; reset function JTDI; alternate functions TIM2_CH1_ETR, SPI1_NSS, SPI3_NSS, I2S3_WS, LCD_SEG17. |
| 78 | PC10 | bidirectional | 5 V tolerant (FT) I/O; reset function PC10; alternate functions SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, LCD_SEG28, LCD_SEG40, LCD_COM4. |
| 79 | PC11 | bidirectional | 5 V tolerant (FT) I/O; reset function PC11; alternate functions SPI3_MISO, USART3_RX, UART4_RX, LCD_SEG29, LCD_SEG41, LCD_COM5. |
| 80 | PC12 | bidirectional | 5 V tolerant (FT) I/O; reset function PC12; alternate functions SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, LCD_SEG30, LCD_SEG42, LCD_COM6. |
| 81 | PD0 | bidirectional | 5 V tolerant (FT) I/O; reset function PD0; alternate functions TIM9_CH1, SPI2_NSS, I2S2_WS. |
| 82 | PD1 | bidirectional | 5 V tolerant (FT) I/O; reset function PD1; alternate functions SPI2_SCK, I2S2_CK. |
| 83 | PD2 | bidirectional | 5 V tolerant (FT) I/O; reset function PD2; alternate functions TIM3_ETR, UART5_RX, LCD_SEG31, LCD_SEG43, LCD_COM7. |
| 84 | PD3 | bidirectional | 5 V tolerant (FT) I/O; reset function PD3; alternate functions SPI2_MISO, USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant (FT) I/O; reset function PD4; alternate functions SPI2_MOSI, I2S2_SD, USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant (FT) I/O; reset function PD5; alternate function USART2_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant (FT) I/O; reset function PD6; alternate function USART2_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant (FT) I/O; reset function PD7; alternate functions TIM9_CH2, USART2_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant (FT) I/O; reset function JTDO; alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, I2S3_CK, LCD_SEG7; additional function COMP2_INM. |
| 90 | PB4 | bidirectional | 5 V tolerant (FT) I/O; reset function NJTRST; alternate functions TIM3_CH1, SPI1_MISO, SPI3_MISO, LCD_SEG8; additional function COMP2_INP. |
| 91 | PB5 | bidirectional | 5 V tolerant (FT) I/O; reset function PB5; alternate functions TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, I2S3_SD, LCD_SEG9; additional function COMP2_INP. |
| 92 | PB6 | bidirectional | 5 V tolerant (FT) I/O; reset function PB6; alternate functions TIM4_CH1, I2C1_SCL, USART1_TX; additional function COMP2_INP. |
| 93 | PB7 | bidirectional | 5 V tolerant (FT) I/O; reset function PB7; alternate functions TIM4_CH2, I2C1_SDA, USART1_RX; additional functions COMP2_INP, PVD_IN. |
| 94 | BOOT0 | input | Dedicated BOOT0 pin used for boot mode selection. |
| 95 | PB8 | bidirectional | 5 V tolerant (FT) I/O; reset function PB8; alternate functions TIM4_CH3, TIM10_CH1, I2C1_SCL, LCD_SEG16. |
| 96 | PB9 | bidirectional | 5 V tolerant (FT) I/O; reset function PB9; alternate functions TIM4_CH4, TIM11_CH1, I2C1_SDA, LCD_COM3. |
| 97 | PE0 | bidirectional | 5 V tolerant (FT) I/O; reset function PE0; alternate functions TIM4_ETR, TIM10_CH1, LCD_SEG36. |
| 98 | PE1 | bidirectional | 5 V tolerant (FT) I/O; reset function PE1; alternate functions TIM11_CH1, LCD_SEG37. |
| 99 | VSS_3 | power_in | Ground pin of the digital domain. |
| 100 | VDD_3 | power_in | Digital supply pin; device supply range is 1.65 V to 3.6 V per the feature list. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32L151VDT7X - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32l151vdt7x-etched.step/stm32l151vdt7x-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l151vdt7x.step/stm32l151vdt7x.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (119 pp, sha256
245e0b433e2986d0, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).