component
LGS5160C
Public Made by Adomby adom
Legend-Si DC-DC Converters, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLGS5160C
Legend-Si · DC-DC Converters · ESOP-8
LGS5160C from Legend-Si, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Internal power switch node that connects to the external power inductor and the CBST capacitor. |
| 2 | BST | power_out | Self-driving bootstrap supply for the high-side gate driver, requiring a high-quality ceramic capacitor of at least 100nF between BST and SW; the BST-to-SW voltage is limited to -0.3V to 5.5V. |
| 3 | VCC | power_out | Output of the internal LDO that powers the control circuits, requiring a 1uF to 4.7uF ceramic decoupling capacitor between VCC and GND placed as close as possible to the pins; the VCC pin voltage is limited to -0.3V to 5.5V. |
| 4 | FREQ | input | Switching frequency setting pin, where a resistor connected from FREQ to GND sets the switching frequency between 200kHz and 2MHz; the pin voltage is limited to -0.3V to 5.5V. |
| 5 | FB | input | Output voltage feedback pin, where an external divider between VOUT and GND sets the output voltage against a 1.0V feedback reference (0.99V to 1.01V), with recommended operating range -0.3V to 1.1V. |
| 6 | PG | output | Open-drain power-good indicator that stops pulling down when the output is normal, to be pulled up to VCC through a 10kΩ to 100kΩ resistor; recommended voltage range is -0.3V to 30V. |
| 7 | EN | input | Enable pin that sets the regulator output enable when high, with a high logic threshold of 1.1V and a low logic threshold of 0.5V, and a recommended range of -0.3V to 65V; an external resistor divider can set VIN undervoltage protection. |
| 8 | VIN | power_in | Input power pin feeding the upper bridge power MOSFET and the VIN linear supply, requiring one or more decoupling ceramic capacitors between VIN and GND placed close to the pins; recommended input range is 4.5V to 65V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Legend-Si |
| Package | ESOP-8 |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Recommended input voltage range | VIN | 4.5 | 65 | V | 7 | ||
| VCC output voltage | VCC | 4.8 | 5 | 5.2 | V | VIN=24V | 7 |
| FB feedback voltage | VFB_acc | 0.99 | 1 | 1.01 | V | 7 | |
| Upper pipe RDSON | RDS_HS | 130 | 160 | mΩ | TJ= 25 | 7 | |
| Lower pipe RDSON | RDS_LS | 95 | 130 | mΩ | TJ= 25 | 7 | |
| Switching frequency accuracy | FSW | 0.9 | 1 | 1.1 | MHz | PWM Operation; RFREQ = 162k | 7 |
| Switching frequency range | FSW_range | 0.2 | 2 | MHz | with 1% RFREQ | 7 | |
| EN undervoltage protection rising edge | VEN_UV_R | 1.19 | 1.2 | 1.21 | V | 7 | |
| EN undervoltage protection falling edge | VEN_UV_F | 1.14 | 1.15 | 1.16 | V | 7 | |
| PG undervoltage drop threshold | VPG_UV | 83 | 85 | 87 | % VFB | 7 | |
| PG overvoltage rise threshold | VPG_OV | 112 | 115 | 118 | % VFB | 7 | |
| Pin to GND voltage (VIN, SW, EN) | -0.3 | 80 | V | 5 | |||
| Pin to SW voltage (BST) | BST | -0.3 | 5.5 | V | 5 | ||
| Pin to GND voltage (FB, FREQ, VCC) | -0.3 | 5.5 | V | 5 | |||
| Pin to GND voltage (PG) | PG | -0.3 | 36 | V | 5 | ||
| ESD rating (HBM) | -2 | 2 | KV | 5 | |||
| ESD rating (CDM) | -1 | 1 | KV | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Work completion temperature (absolute maximum) | -40 | 150 | °C | 5 | |||
| VIN recommended range | VIN | 4.5 | 65 | V | 5 | ||
| EN voltage | EN | -0.3 | 65 | V | 5 | ||
| FB voltage | FB | -0.3 | 1.1 | V | 5 | ||
| PG voltage | PG | -0.3 | 30 | V | 5 | ||
| Output voltage | VOUT | 1 | V | Maximum is VIN (printed as 1V~VIN) | 5 | ||
| Output current | IOUT | 0 | 3 | A | 5 | ||
| Work completion temperature (recommended operating) | -40 | 125 | °C | 5 | |||
| IFB leakage current | IFB_leak | 80 | nA | 7 | |||
| FB jump cycle threshold | VFB_skip | 1.003 | V | 7 | |||
| VIN undervoltage protection threshold (rising) | VIN_GD | 4 | V | Rising | 7 | ||
| VIN undervoltage protection threshold (falling) | VIN_GD | 3.6 | V | Falling | 7 | ||
| VIN equivalent static current | IQ | 130 | uA | VIN=24V, VFB=1.2V; No switch | 7 | ||
| VCC undervoltage protection (rising) | VCC_GD | 3.5 | V | Rising | 7 | ||
| VCC undervoltage protection (falling) | VCC_GD | 3.2 | V | Falling | 7 | ||
| VCC short-circuit current (VIN power supply) | ISC_VCC | 20 | mA | VIN=24V | 7 | ||
| Upper tube current limit | lPeak_HS | 3.7 | A | 7 | |||
| Lower tube current limit | IPeak_LS | 3.3 | A | 7 | |||
| Zero crossing of lower tube current | IZCD | 50 | mA | 7 | |||
| SW leakage current | ISW.LKG | 1 | uA | 7 | |||
| Minimum conduction time of upper tube | THSON.MIN | 90 | ns | 7 | |||
| Minimum conduction time of the lower tube | TLSON.MIN | 160 | ns | 7 | |||
| Short circuit protection triggering time | TSCP_HOLD | 5 | ms | 7 | |||
| Short circuit protection hiccup waiting time | TSCP_HICCUP | 4 | ms | 7 | |||
| EN high logic threshold | VEN_H | 1.1 | V | 7 | |||
| EN low logic threshold | VEN_L | 0.5 | V | 7 | |||
| EN input current | ILKG-EN | 1 | uA | EN < 65V | 7 | ||
| PG undervoltage recovery hysteresis loop | 2 | % VFB | 7 | ||||
| PG overvoltage recovery hysteresis loop | 1 | % VFB | 8 | ||||
| Over Temperature Protection (rising) | TOTP-R | 160 | °C | TJ Rising | 8 | ||
| Over temperature protection released (falling) | TOTP-F | 145 | °C | TJ Falling | 8 | ||
| Thermal resistance, silicon core to surrounding air | θJA | 42.9 | °C/W | 0 LFPM Air Flow | 8 | ||
| Thermal resistance, silicon core to PCB board surface | θJB | 13.6 | °C/W | 8 | |||
| Thermal resistance, silicon core to packaging surface | θJCtop | 54 | °C/W | 8 | |||
| Thermal resistance, silicon core to PCB board surface | ΨJB | 13.8 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
LGS5160C - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
lgs5160c-etched.step/lgs5160c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lgs5160c.step/lgs5160c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Legend-Si datasheet (25 pp, sha256
92c4a89ba3643f4e, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).