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Contents

Pinout
Key specifications
Electrical characteristics
Materials and finish
CAD (KiCad official)
Provenance

README

markdown

SI52147-A01AGMR

SILICON LABS · Clock Generators / Frequency Synthesizers / PLL · QFN-48-EP(6x6)

SI52147-A01AGMR from SILICON LABS, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
2	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
3	OE_DIFF0	input	Active high input pin enables DIFF0, with internal 100 kΩ pull-up.
4	OE_DIFF1	input	Active high input pin enables DIFF1, with internal 100 kΩ pull-up.
5	SSON	input	Active high input pin enables -0.5% spread on DIFF clocks, with internal 100 kΩ pull-down.
6	VSS_DIFF	power_in	Ground.
7	VSS_DIFF	power_in	Ground.
8	OE_DIFF2	input	Active high input pin enables DIFF2, with internal 100 kΩ pull-up.
9	OE_DIFF3	input	Active high input pin enables DIFF3, with internal 100 kΩ pull-up.
10	OE_DIFF[4:5]	input	Active high input pin enables DIFF[4:5], with internal 100 kΩ pull-up.
11	OE_DIFF[6:8]	input	Active high input pin enables DIFF[6:8], with internal 100 kΩ pull-up.
12	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
13	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
14	DIFF0	output	0.7 V, 100 MHz differential clock output (one half of the DIFF0 pair).
15	DIFF0	output	0.7 V, 100 MHz differential clock output (one half of the DIFF0 pair).
16	VSS_DIFF	power_in	Ground.
17	DIFF1	output	0.7 V, 100 MHz differential clock output (one half of the DIFF1 pair).
18	DIFF1	output	0.7 V, 100 MHz differential clock output (one half of the DIFF1 pair).
19	DIFF2	output	0.7 V, 100 MHz differential clock output (one half of the DIFF2 pair).
20	DIFF2	output	0.7 V, 100 MHz differential clock output (one half of the DIFF2 pair).
21	DIFF3	output	0.7 V, 100 MHz differential clock output (one half of the DIFF3 pair).
22	DIFF3	output	0.7 V, 100 MHz differential clock output (one half of the DIFF3 pair).
23	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
24	VSS_DIFF	power_in	Ground.
25	DIFF4	output	0.7 V, 100 MHz differential clock output (one half of the DIFF4 pair).
26	DIFF4	output	0.7 V, 100 MHz differential clock output (one half of the DIFF4 pair).
27	DIFF5	output	0.7 V, 100 MHz differential clock output (one half of the DIFF5 pair).
28	DIFF5	output	0.7 V, 100 MHz differential clock output (one half of the DIFF5 pair).
29	VSS_DIFF	power_in	Ground.
30	DIFF6	output	0.7 V, 100 MHz differential clock output (one half of the DIFF6 pair).
31	DIFF6	output	0.7 V, 100 MHz differential clock output (one half of the DIFF6 pair).
32	DIFF7	output	0.7 V, 100 MHz differential clock output (one half of the DIFF7 pair).
33	DIFF7	output	0.7 V, 100 MHz differential clock output (one half of the DIFF7 pair).
34	VDD_DIFF	power_in	3.3 V power supply for the DIFF clock outputs (3.135 to 3.465 V).
35	DIFF8	output	0.7 V, 100 MHz differential clock output (one half of the DIFF8 pair).
36	DIFF8	output	0.7 V, 100 MHz differential clock output (one half of the DIFF8 pair).
37	SCLK	input	I2C compatible SCLOCK input (VIH 2.2 V min, VIL 1.0 V max).
38	SDATA	bidirectional	I2C compatible SDATA input/output (VIH 2.2 V min, VIL 1.0 V max).
39	CKPWRGD/PDB	input	Active low input pin asserts power down (PDB) and disables all outputs, with internal 100 kΩ pull-up; must be driven at all times.
40	VDD_CORE	power_in	3.3 V power supply for the core (3.135 to 3.465 V).
41	XOUT	output	25.00 MHz crystal output; float XOUT if using only CLKIN (clock input).
42	XIN/CLKIN	input	25.00 MHz crystal input or 3.3 V, 25 MHz clock input.
43	NC	unconnected	No connect.
44	NC	unconnected	No connect.
45	VSS_CORE	power_in	Ground.
46	VSS_DIFF	power_in	Ground.
47	NC	unconnected	No connect.
48	NC	unconnected	No connect.
49	GND	power_in	Ground for bottom pad of the IC.

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	QFN-48-EP(6x6)
Category	Clock and Timing
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
3.3 V Operating Voltage	VDD core	3.135	3.3	3.465	V	3.3 ±5%	4
3.3 V Input High Voltage	VIH	2			V	Control input pins (max VDD + 0.3 V)	4
3.3 V Input Low Voltage	VIL			0.8	V	Control input pins (min VSS, 0.3 V)	4
Input High Voltage I2C	VIHI2C	2.2			V	SDATA, SCLK	4
Input Low Voltage I2C	VILI2C			1	V	SDATA, SCLK	4
Input High Leakage Current	IIH			5	A	Except internal pull-down resistors, 0 < VIN < VDD	4
Input Low Leakage Current	IIL	-5			A	Except internal pull-up resistors, 0 < VIN < VDD	4
High-impedance Output Current	IOZ	-10		10	A		4
Input Pin Capacitance	CIN	1.5		5	pF		4
Output Pin Capacitance	COUT			6	pF		4
Pin Inductance	LIN			7	nH		4
Power Down Current	IDD_PD			1	mA		4
Dynamic Supply Current	IDD_3.3V			85	mA	All outputs enabled. Differential clocks with 5” traces and 2 pF load.	4
Crystal Long-term Accuracy	LACC			250	ppm	Measured at VDD/2 differential	5
CLKIN Duty Cycle	TDC	47		53	%	Measured at VDD/2	5
CLKIN Rise and Fall Times	TR/TF	0.5		4	V/ns	Measured between 0.2 VDD and 0.8 VDD	5
CLKIN Cycle to Cycle Jitter	TCCJ			250	ps	Measured at VDD/2	5
CLKIN Long Term Jitter	TLTJ			350	ps	Measured at VDD/2	5
XIN/CLKIN Input High Voltage	VIH	2			V	XIN/CLKIN pin (max VDD+0.3 V)	5
XIN/CLKIN Input Low Voltage	VIL			0.8	V	XIN/CLKIN pin	5
XIN/CLKIN Input High Current	IIH			35	uA	XIN/CLKIN pin, VIN = VDD	5
XIN/CLKIN Input Low Current	IIL	-35			uA	XIN/CLKIN pin, 0 < VIN <0.8	5
DIFF Duty Cycle	TDC	45		55	%	Measured at 0 V differential	5
Output-to-Output skew	TSKEW			800	ps	Measured at 0 V differential	5
DIFF Cycle to Cycle Jitter	TCCJ		35	50	ps	Measured at 0 V differential	5
PCIe Gen 1 Pk-Pk Jitter, Common Clock	Pk-Pk	0	40	50	ps	PCIe Gen 1	5
PCIe Gen 2 Phase Jitter, Common Clock	RMSGEN2	0	1.8	2	ps	10 kHz < F < 1.5 MHz	5
PCIe Gen 2 Phase Jitter, Common Clock	RMSGEN2	0	1.8	2.1	ps	1.5 MHz < F < Nyquist	5
PCIe Gen 3 Phase Jitter, Common Clock	RMSGEN3	0	0.5	0.6	ps	PLL BW of 2-4 or 2-5 MHz, CDR = 10 MHz	5
PCIe Gen 3 Phase Jitter, SRNS	RMSGEN3_SRNS		0.35	0.42	ps	PLL BW of 2-4 or 2-5 MHz, CDR = 10 MHz	5
PCIe Gen 4 Phase Jitter, Common Clock	RMSGEN4		0.5	0.6	ps	PLL BW of 2-4 or 2-5 MHz, CDR = 10 MHz	5
DIFF Long Term Accuracy	LACC			100	ppm	Measured at 0 V differential	5
Rising/Falling Slew Rate	TR/TF	1		8	V/ns	Measured differentially from ±150 mV	5
Voltage High	VHIGH			1.15	V		5
Voltage Low	VLOW	-0.3			V		5
Crossing Point Voltage at 0.7 V Swing	VOX	300		550	mV		5
Spread Range	SPR		-0.5		%	Down spread	5
Modulation Frequency	FMOD	30	31.5	33	kHz		5
Clock Stabilization from Power-up	TSTABLE			1.8	ms	Measured from the point both VDD and clock input are valid	6
Stopclock Set-up Time	TSS	10			ns		6
Main Supply Voltage	VDD_3.3V			4.6	V	Functional	6
Input Voltage	VIN	-0.5		4.6	VDC	Relative to VSS	6
Temperature, Storage	TS	-65		150	°C	Non-functional	6
Temperature, Operating Ambient	TA	-40		85	°C	Functional	6
Temperature, Junction	TJ			150	°C	Functional	6
Dissipation, Junction to Case	ØJC			22	°C/W	JEDEC (JESD 51)	6
Dissipation, Junction to Ambient	ØJA			30	°C/W	JEDEC (JESD 51)	6
ESD Protection (Human Body Model)	ESDHBM	2000			V	JEDEC (JESD 22-A114)	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.	5

CAD (KiCad official)

Symbol: SI52147-A01AGMR
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: si52147-a01agmr-etched.step / si52147-a01agmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si52147-a01agmr.step / si52147-a01agmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (25 pp, sha256 9982bf765a362a6e, retrieved 2026-10-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF