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TPS78925DBVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps78925dbvrfactory-2.0.0extractor-text

Verified TPS78925DBVR

by Ray · last 5 Nov 2026 · 1 record · files match
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Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS78925DBVR · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2877748, digikey 296-TPS78925DBVRTR-ND, mouser 595-TPS78925DBVR
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-gfb94cf_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps78925dbvr.kicad_sym✓ tps78925dbvr.kicad_mod✓ tps78925dbvr.step
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Contents

README

markdown

TPS78925DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS78925DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input The IN terminal is the input to the device, with a recommended input voltage range of 2.7 V to 10 V and VI(min) equal to VO(max) plus the dropout voltage at maximum load.
2 GND power_in Regulator ground, which also carries the quiescent current; the output capacitor must connect between OUT and GND with a minimum of 4.7 µF.
3 EN input Active low enable: a voltage of 1.7 V or greater disables the device and a voltage below 0.9 V enables it.
4 BYPASS input The external bypass capacitor, in conjunction with an internal 150-kΩ resistor, creates a low-pass filter to further reduce regulator noise.
5 OUT output The OUT terminal is the regulated output of the device, rated up to 100 mA continuous output current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage, VI VI 2.7 10 V 4
Continuous output current, IO IO 0 100 mA 4
Operating junction temperature, TJ TJ -40 125 °C 4
Input voltage range -0.3 13.5 V 3
Voltage range at EN EN -0.3 V max VI + 0.3 V 3
Voltage on OUT OUT 7 V 3
ESD rating, HBM 2 kV 3
Operating virtual junction temperature range, TJ TJ -40 150 °C 3
Storage temperature range, Tstg Tstg -65 150 °C 3
Output voltage VO 2.425 2.575 V TJ = -40°C to 125°C, 3.5 V < VI < 10 V 4
Output voltage VO 2.5 V TJ = 25°C, 3.5 V < VI < 10 V 4
Quiescent current (GND current) 28 µA EN = 0 V, IO = 100 mA, TJ = -40°C to 125°C 4
Quiescent current (GND current) 17 µA EN = 0 V, 10 µA < IO < 100 mA, TJ = 25°C 4
Output current limit 350 750 mA VO = 0 V, See Note 4 4
Standby current 1 µA EN = VI, 2.7 < VI < 10 V 4
Standby current 2 µA TJ = -40°C to 125°C 4
High level enable input voltage 1.7 V 2.7 V < VI < 10 V 5
Low level enable input voltage 0.9 V 2.7 V < VI < 10 V 5
Input current (EN) -1 0 1 µA EN = 0 V 5
Input current (EN) -1 1 µA EN = VI 5
Output voltage line regulation (∆VO/VO) 0.04 %/V VO + 1 V < VI ≤ 10 V, TJ = 25°C, See Note 4 4
Output voltage line regulation (∆VO/VO) 0.1 %/V VO + 1 V < VI ≤ 10 V, TJ = -40°C to 125°C, See Note 4 4
Load regulation 12 mV EN = 0 V, IO = See Note 4, TJ = 25°C 4
Junction-to-case thermal resistance, RθJC RθJC 65.8 °C/W DBV package 3
Junction-to-ambient thermal resistance, RθJA (Low K) RθJA 259 °C/W JEDEC Low K (1s) board 3
Junction-to-ambient thermal resistance, RθJA (High K) RθJA 180 °C/W JEDEC High K (2s2p) board 3
Derating factor above TA = 25°C (Low K) 3.9 mW/°C Low K board, TA > 25°C 3
Derating factor above TA = 25°C (High K) 5.6 mW/°C High K board, TA > 25°C 3

CAD (KiCad official)

  • Symbol: TPS78925DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps78925dbvr-etched.step / tps78925dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps78925dbvr.step / tps78925dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 f216afa23ba1c3fd, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF