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STM32F215VET6

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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Contents

README

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STM32F215VET6

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

STM32F215VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant I/O (FT) with alternate functions TRACECLK, FSMC_A23, ETH_MII_TXD3 and EVENTOUT; floating input during and after reset unless a note says otherwise.
2 PE3 bidirectional 5 V-tolerant I/O (FT) with alternate functions TRACED0, FSMC_A19 and EVENTOUT; floating input during and after reset unless a note says otherwise.
3 PE4 bidirectional 5 V-tolerant I/O (FT) with alternate functions TRACED1, FSMC_A20, DCMI_D4 and EVENTOUT; floating input during and after reset unless a note says otherwise.
4 PE5 bidirectional 5 V-tolerant I/O (FT) with alternate functions TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6 and EVENTOUT; floating input during and after reset unless a note says otherwise.
5 PE6 bidirectional 5 V-tolerant I/O (FT) with alternate functions TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7 and EVENTOUT; floating input during and after reset unless a note says otherwise.
6 VBAT power_in Backup supply for the RTC, the 20 x 32-bit backup registers and the optional 4 Kbyte backup SRAM.
7 PC13 bidirectional I/O supplied through the power switch, which sinks only 3 mA, so the speed must not exceed 2 MHz with a 30 pF load and the pin must not drive LEDs or act as a current source; additional function RTC_AF1.
8 PC14/OSC32_IN bidirectional I/O supplied through the power switch (3 mA sink limit, maximum 2 MHz at 30 pF, not to be used as a current source) that is also the 32 kHz oscillator input OSC32_IN.
9 PC15/OSC32_OUT bidirectional I/O supplied through the power switch (3 mA sink limit, maximum 2 MHz at 30 pF, not to be used as a current source) that is also the 32 kHz oscillator output OSC32_OUT.
10 VSS power_in Digital ground pin (VSS) of the MCU.
11 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.
12 PH0/OSC_IN bidirectional 5 V-tolerant I/O (FT) except in oscillator mode, used as the 4 to 26 MHz crystal oscillator input OSC_IN; alternate function EVENTOUT.
13 PH1/OSC_OUT bidirectional 5 V-tolerant I/O (FT) except in oscillator mode, used as the 4 to 26 MHz crystal oscillator output OSC_OUT; alternate function EVENTOUT.
14 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor; VIL(NRST) and VIH(NRST) are specified in Table 48.
15 PC0 bidirectional 5 V-tolerant I/O (FT) with alternate function OTG_HS_ULPI_STP and EVENTOUT, and analog input ADC123_IN10.
16 PC1 bidirectional 5 V-tolerant I/O (FT) with alternate function ETH_MDC and EVENTOUT, and analog input ADC123_IN11.
17 PC2 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2 and EVENTOUT, and analog input ADC123_IN12.
18 PC3 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK and EVENTOUT, and analog input ADC123_IN13.
19 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.
20 VSSA power_in Dedicated analog ground pin (VSSA) for the analog circuitry.
21 VREF+ power_in Positive reference voltage for the ADC; may be connected to VDDA or decoupled separately as shown in Figures 52 and 53.
22 VDDA power_in Analog supply pin (VDDA); decoupling is shown in Figures 52 and 53.
23 PA0/WKUP bidirectional 5 V-tolerant I/O (FT) with alternate functions USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and EVENTOUT, analog input ADC123_IN0 and wakeup function WKUP.
24 PA1 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2 and EVENTOUT, and analog input ADC123_IN1.
25 PA2 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO and EVENTOUT, and analog input ADC123_IN2.
26 PA3 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL and EVENTOUT, and analog input ADC123_IN3.
27 VSS power_in Digital ground pin (VSS) of the MCU.
28 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.
29 PA4 bidirectional 3.3 V-tolerant I/O (TTa) with alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS and EVENTOUT, analog input ADC12_IN4 and DAC output DAC_OUT1.
30 PA5 bidirectional 3.3 V-tolerant I/O (TTa) with alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N and EVENTOUT, analog input ADC12_IN5 and DAC output DAC_OUT2.
31 PA6 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN and EVENTOUT, and analog input ADC12_IN6.
32 PA7 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV and EVENTOUT, and analog input ADC12_IN7.
33 PC4 bidirectional 5 V-tolerant I/O (FT) with alternate functions ETH_RMII_RXD0 / ETH_MII_RXD0 and EVENTOUT, and analog input ADC12_IN14.
34 PC5 bidirectional 5 V-tolerant I/O (FT) with alternate functions ETH_RMII_RXD1 / ETH_MII_RXD1 and EVENTOUT, and analog input ADC12_IN15.
35 PB0 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N and EVENTOUT, and analog input ADC12_IN8.
36 PB1 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N and EVENTOUT, and analog input ADC12_IN9.
37 PB2/BOOT1 bidirectional 5 V-tolerant I/O (FT) with alternate function EVENTOUT; the pin is also named BOOT1 in the table.
38 PE7 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D4, TIM1_ETR and EVENTOUT.
39 PE8 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D5, TIM1_CH1N and EVENTOUT.
40 PE9 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D6, TIM1_CH1 and EVENTOUT.
41 PE10 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D7, TIM1_CH2N and EVENTOUT.
42 PE11 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D8, TIM1_CH2 and EVENTOUT.
43 PE12 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D9, TIM1_CH3N and EVENTOUT.
44 PE13 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D10, TIM1_CH3 and EVENTOUT.
45 PE14 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D11, TIM1_CH4 and EVENTOUT.
46 PE15 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D12, TIM1_BKIN and EVENTOUT.
47 PB10 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_SCK, I2S2_SCK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3 and EVENTOUT.
48 PB11 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TIM2_CH4 and EVENTOUT.
49 VCAP_1 power_in Internal regulator output pin VCAP_1 that requires an external VCAP1/VCAP2 capacitor as specified in section 6.3.2.
50 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID and EVENTOUT.
52 PB13 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_SCK, I2S2_SCK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1, ETH_MII_TXD1 and EVENTOUT; additional function OTG_HS_VBUS.
53 PB14 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N and EVENTOUT.
54 PB15 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, RTC_50Hz and EVENTOUT.
55 PD8 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D13, USART3_TX and EVENTOUT.
56 PD9 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D14, USART3_RX and EVENTOUT.
57 PD10 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D15, USART3_CK and EVENTOUT.
58 PD11 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_A16, USART3_CTS and EVENTOUT.
59 PD12 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_A17, TIM4_CH1, USART3_RTS and EVENTOUT.
60 PD13 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_A18, TIM4_CH2 and EVENTOUT.
61 PD14 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D0, TIM4_CH3 and EVENTOUT.
62 PD15 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D1, TIM4_CH4 and EVENTOUT.
63 PC6 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1 and EVENTOUT.
64 PC7 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2 and EVENTOUT.
65 PC8 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2 and EVENTOUT.
66 PC9 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2S2_CKIN, I2S3_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4 and EVENTOUT.
67 PA8 bidirectional 5 V-tolerant I/O (FT) with alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF and EVENTOUT.
68 PA9 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0 and EVENTOUT; additional function OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1 and EVENTOUT.
70 PA11 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM and EVENTOUT.
71 PA12 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP and EVENTOUT.
72 PA13/JTMS-SWDIO bidirectional 5 V-tolerant I/O (FT) whose function after reset is JTMS-SWDIO, with alternate function EVENTOUT.
73 VCAP_2 power_in Internal regulator output pin VCAP_2 that requires an external VCAP1/VCAP2 capacitor as specified in section 6.3.2.
74 VSS power_in Digital ground pin (VSS) of the MCU.
75 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.
76 PA14/JTCK-SWCLK bidirectional 5 V-tolerant I/O (FT) whose function after reset is JTCK-SWCLK, with alternate function EVENTOUT.
77 PA15/JTDI bidirectional 5 V-tolerant I/O (FT) whose function after reset is JTDI, with alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS and EVENTOUT.
78 PC10 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI3_SCK, I2S3_SCK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX and EVENTOUT.
79 PC11 bidirectional 5 V-tolerant I/O (FT) with alternate functions UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and EVENTOUT.
80 PC12 bidirectional 5 V-tolerant I/O (FT) with alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD, USART3_CK and EVENTOUT.
81 PD0 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D2, CAN1_RX and EVENTOUT.
82 PD1 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_D3, CAN1_TX and EVENTOUT.
83 PD2 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11 and EVENTOUT.
84 PD3 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_CLK, USART2_CTS and EVENTOUT.
85 PD4 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_NOE, USART2_RTS and EVENTOUT.
86 PD5 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_NWE, USART2_TX and EVENTOUT.
87 PD6 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_NWAIT, USART2_RX and EVENTOUT.
88 PD7 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART2_CK, FSMC_NE1, FSMC_NCE2 and EVENTOUT.
89 PB3/JTDO/TRACESWO bidirectional 5 V-tolerant I/O (FT) whose function after reset is JTDO/TRACESWO, with alternate functions SPI3_SCK, I2S3_SCK, TIM2_CH2, SPI1_SCK and EVENTOUT.
90 PB4 bidirectional 5 V-tolerant I/O (FT) with alternate functions NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO and EVENTOUT.
91 PB5 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10, I2S3_SD and EVENTOUT.
92 PB6 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX and EVENTOUT.
93 PB7 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C1_SDA, FSMC_NL (also named FSMC_NADV on memory devices), DCMI_VSYNC, USART1_RX, TIM4_CH2 and EVENTOUT.
94 BOOT0 input Dedicated BOOT0 boot-mode input pin (input only, B structure) that also carries the VPP function for Flash programming with VPP.
95 PB8 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX and EVENTOUT.
96 PB9 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX and EVENTOUT.
97 PE0 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM4_ETR, FSMC_NBL0, DCMI_D2 and EVENTOUT.
98 PE1 bidirectional 5 V-tolerant I/O (FT) with alternate functions FSMC_NBL1, DCMI_D3 and EVENTOUT.
99 RFU unconnected Reserved for future use; this pin can be tied to VDD, VSS or left unconnected.
100 VDD power_in Digital supply pin; application supply and I/Os range from 1.8 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

CAD (KiCad official)

  • Symbol: STM32F215VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f215vet6-etched.step / stm32f215vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f215vet6.step / stm32f215vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (180 pp, sha256 081e0a9e956467f5, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF