component
A6986TR
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownA6986TR
STMicroelectronics · DC-DC Converters · TSSOP-16
A6986TR from STMicroelectronics, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST | output | Open-collector reset output that is driven low when the output voltage is out of regulation and is released after an adjustable DELAY time once the output is over the active delay threshold. |
| 2 | VCC | power_out | Connect a ceramic capacitor of at least 470 nF to filter the internal voltage reference; this pin supplies the embedded analog circuitry. |
| 3 | SS/INH | bidirectional | Clamping this pin to GND disables the device (INH mode), and an internal current generator of 4 A typ. charges the external capacitor to implement the soft-start. |
| 4 | SYNCH | input | Master/slave synchronization pin for LNM operation; leave floating when not used. |
| 5 | FSW | input | A pull-up resistor (E24 series only) to VCC or a pull-down to GND selects the switching frequency, and pin strapping is active only before the soft-start phase. |
| 6 | MLF | input | A pull-up resistor (E24 series only) to VCC or a pull-down to GND selects low noise mode/low consumption mode and the active RST threshold, and pin strapping is active only before the soft-start phase. |
| 7 | COMP | passive | Output of the error amplifier, to which the designed compensation network is connected. |
| 8 | DELAY | passive | An external capacitor sets the time DELAY to assert the rising edge of RST after the output voltage is over the reset threshold; if left floating, RST behaves like a power good. |
| 9 | FB | input | Inverting input of the error amplifier. |
| 10 | SGND | power_in | Signal ground; the exposed pad must be connected to SGND and PGND. |
| 11 | PGND | power_in | Power ground. |
| 12 | PGND | power_in | Power ground. |
| 13 | LX | output | Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V. |
| 14 | LX | output | Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V. |
| 15 | VIN | power_in | DC input voltage, with an operating input range of 4 V to 38 V. |
| 16 | VBIAS | power_in | Typically connected to the regulated output voltage to supply part of the analog circuitry for better light-load efficiency; connect to GND if not used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
A6986TR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
a6986tr-etched.step/a6986tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a6986tr.step/a6986tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (68 pp, sha256
2108f535617ad184, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).