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TLP352
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TOSHIBA Logic Output Optoisolators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLP352
TOSHIBA · Logic Output Optoisolators · DIP-8
TLP352 from TOSHIBA, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N.C. | unconnected | Not connected; the datasheet lists this pin as N.C. in the pin assignment. |
| 2 | Anode | input | LED anode of the input photodiode; the absolute maximum input forward current is 20 mA and the threshold input current (L/H) is 5 mA max. |
| 3 | Cathode | input | LED cathode of the input; drive the LED within the 20 mA absolute maximum forward current and the 5 mA maximum threshold input current. |
| 4 | N.C. | unconnected | Not connected; the datasheet lists this pin as N.C. in the pin assignment. |
| 5 | GND | power_in | Detector ground reference; a 0.1 µF ceramic bypass capacitor must be connected between pin 8 and pin 5, placed within 1 cm of each pin. |
| 6 | VO | output | Totem-pole output that can both sink and source current, with peak output current limited to ±2.5 A (max). |
| 7 | N.C. | unconnected | Not connected; the datasheet lists this pin as N.C. in the pin assignment. |
| 8 | VCC | power_in | Detector supply pin with an operating supply voltage of 15 to 30 V; the rising VCC slope must be 3.0 V/µs or less and a 0.1 µF bypass to pin 5 is required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | DIP-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input forward current | IF | 20 | mA | 4 | |||
| Peak high-level output current | IOPH | -2.5 | A | Ta = -40 to 125 | 4 | ||
| Peak low-level output current | IOPL | 2.5 | A | Ta = -40 to 125 | 4 | ||
| Input power dissipation | PD | 40 | mW | 4 | |||
| Output voltage | VO | 35 | V | 4 | |||
| Supply voltage | VCC | 35 | V | 4 | |||
| Output power dissipation | PO | 260 | mW | 4 | |||
| Operating temperature | Topr | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Lead soldering temperature | Tsol | 260 | °C | 10 s | 4 | ||
| Isolation voltage | BVS | 3750 | Vrms | AC, 60 s, R.H. ≤ 60 % | 4 | ||
| Input on-state current | IF(ON) | 6.5 | 10 | mA | Rise and fall times of input on-current < 0.5 µs | 5 | |
| Input off-state voltage | VF(OFF) | 0.8 | V | 5 | |||
| Supply voltage | VCC | 15 | 30 | V | 5 | ||
| Peak high-level output current | IOPH | -2 | A | Exponential waveform, ≤ 0.3 µs, Ta = 125 | 5 | ||
| Peak low-level output current | IOPL | 2 | A | Exponential waveform, ≤ 0.3 µs, Ta = 125 | 5 | ||
| Operating frequency | f | 50 | kHz | 5 | |||
| Input forward voltage | VF | 1.4 | 1.55 | 1.7 | V | IF = 10 mA, Ta = 25 | 5 |
| Input reverse current | IR | 10 | µA | VR = 5 V, Ta = 25 | 5 | ||
| High-level supply current | ICCH | 3 | mA | IF = 10 mA, VCC = 30 V, VO = Open | 5 | ||
| Low-level supply current | ICCL | 3.05 | mA | IF = 0 mA, VCC = 30 V, VO = Open | 5 | ||
| Supply voltage | VCC | 15 | 30 | V | 5 | ||
| UVLO threshold voltage (VUVLO+) | VUVLO+ | 11 | 12.5 | 13.5 | V | VCC = 15 V, VO > 1 V | 5 |
| UVLO threshold voltage (VUVLO-) | VUVLO- | 9.5 | 11 | 12 | V | VCC = 15 V, VO < 1 V | 5 |
| Common-mode transient immunity at output high | CMH | 20 | kV/µs | VCM = 1000 Vp-p, IF = 5 mA, VCC = 30 V, Ta = 25, VO(min) = 26 V | 6 | ||
| Common-mode transient immunity at output low | CML | 20 | kV/µs | VCM = 1000 Vp-p, IF = 0 mA, VCC = 30 V, Ta = 25, VO(max) = 1 V | 6 | ||
| Propagation delay time (L/H) | tpLH | 50 | 130 | 200 | ns | IF = 0 → 5 mA, VCC = 30 V, Rg = 20 Ω, Cg = 10 nF | 6 |
| Propagation delay time (H/L) | tpHL | 50 | 130 | 200 | ns | IF = 5 → 0 mA, VCC = 30 V, Rg = 20 Ω, Cg = 10 nF | 6 |
| Pulse width distortion /tpHL-tpLH/ | /tpHL-tpLH/ | 50 | ns | IF = 0 ←→ 5 mA, VCC = 30 V, Rg = 20 Ω, Cg = 10 nF | 6 | ||
| Propagation delay skew (device to device) | tpsk | 80 | ns | IF = 0 ←→ 5 mA, VCC = 30 V, Rg = 20 Ω, Cg = 10 nF | 6 | ||
| Isolation voltage | BVS | 3750 | Vrms | AC, 60 s | 6 | ||
| Input forward voltage temperature coefficient | ΔVF/ΔTa | -2 | mV/°C | IF = 10 mA | 5 | ||
| Input capacitance | CT | 95 | pF | V = 0 V, f = 1 MHz, Ta = 25 | 5 | ||
| Total capacitance (input to output) | CS | 1 | pF | VS = 0 V, f = 1 MHz | 6 | ||
| Input forward current derating | ΔIF/ΔTa | -0.61 | mA/°C | Ta ≥ 116 | 4 | ||
| Input power dissipation derating | ΔPD/ΔTa | -1 | mW/°C | Ta ≥ 110 | 4 | ||
| Output power dissipation derating | ΔPO/ΔTa | -6.5 | mW/°C | Ta ≥ 110 | 4 |
CAD (KiCad official)
- Symbol:
TLP352 - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
tlp352-etched.step/tlp352-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlp352.step/tlp352.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (21 pp, sha256
c400b818a95d56e9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).