component
DAC5573IPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC5573IPWR
Texas Instruments · Digital To Analog Converters (DACs) · TSSOP-16
DAC5573IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A, rail-to-rail buffered output with range 0 to VREFH. |
| 2 | VOUTB | output | Analog output voltage from DAC B, rail-to-rail buffered output with range 0 to VREFH. |
| 3 | VREFH | input | Positive reference voltage input, with input range 0 to VDD. |
| 4 | VDD | power_in | Analog voltage supply input, 2.7 V to 5.5 V (absolute maximum -0.3 V to +6 V relative to GND). |
| 5 | VREFL | input | Negative reference voltage input, with VREFL below VREFH and an input range of GND to VDD/2. |
| 6 | GND | power_in | Ground reference point for all circuitry on the part. |
| 7 | VOUTC | output | Analog output voltage from DAC C, rail-to-rail buffered output with range 0 to VREFH. |
| 8 | VOUTD | output | Analog output voltage from DAC D, rail-to-rail buffered output with range 0 to VREFH. |
| 9 | LDAC | input | Hardware synchronous VOUT update input. |
| 10 | SCL | input | I2C serial clock input, with logic thresholds referenced to IOVDD. |
| 11 | SDA | bidirectional | I2C serial data input/output (device has data transmit capability), with logic thresholds referenced to IOVDD. |
| 12 | IOVDD | power_in | I/O voltage supply input, 2.7 V to 5.5 V, setting the digital input thresholds (0.3xIOVDD low, 0.7xIOVDD high). |
| 13 | A0 | input | Device address select input for the I2C address. |
| 14 | A1 | input | Device address select input for the I2C address. |
| 15 | A2 | input | Device address select input for the extended address. |
| 16 | A3 | input | Device address select input for the extended address. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Converters |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy | 0.25 | 0.5 | LSB | 3 | |||
| Differential nonlinearity | 0.1 | 0.25 | LSB | Specified monotonic by design | 3 | ||
| Zero-scale error | 5 | 20 | mV | 3 | |||
| Full-scale error | -0.15 | 1 | % of FSR | 3 | |||
| Gain error | 1 | % of FSR | 3 | ||||
| Output voltage settling time (full scale) | 6 | 8 | µs | RL = ∞; 0 pF < CL < 200 pF | 3 | ||
| Reference current | 185 | 260 | µA | VREF=VDD = +5 V | 3 | ||
| Reference current | 122 | 200 | µA | VREF=VDD = +3 V | 3 | ||
| Logic input current | -1 | 1 | µA | 3 | |||
| Input low voltage | VIN_L | 0.3 | V | 0.3xIOVDD | 3 | ||
| Input high voltage | VIN_H | 0.7 | V | 0.7xIOVDD | 3 | ||
| Supply voltage | VDD, IOVDD | 2.7 | 5.5 | V | 3 | ||
| IDD normal operation | IDD | 600 | 900 | µA | VDD=+3.6V to +5.5V, VIH=IOVDD and VIL=GND | 3 | |
| IDD normal operation | IDD | 500 | 750 | µA | VDD=+2.7V to +3.6V, VIH=IOVDD and VIL=GND | 3 | |
| IDD power-down | IDD | 0.2 | 1 | µA | VDD=+3.6V to +5.5V, VIH=IOVDD and VIL=GND | 4 | |
| IDD power-down | IDD | 0.05 | 1 | µA | VDD=+2.7V to +3.6V, VIH=IOVDD and VIL=GND | 4 | |
| VDD to GND | VDD | -0.3 | 6 | V | 2 | ||
| Digital input voltage to GND | -0.3 | 6 | V | -0.3 V to VDD + 0.3 V | 2 | ||
| VOUT to GND | VOUT | -0.3 | 6 | V | -0.3 V to VDD + 0.3 V | 2 | |
| Operating temperature range | -40 | 105 | °C | 2 | |||
| Storage temperature range | -65 | 150 | °C | 2 | |||
| Junction temperature | TJ max | 150 | °C | 2 | |||
| Thermal impedance junction-ambient | RΘJA | 161 | °C/W | 2 | |||
| Thermal impedance junction-case | RΘJC | 29 | °C/W | 2 | |||
| Specified performance temperature | -40 | 105 | °C | 4 | |||
| SCL clock frequency | fSCL | 100 | kHz | Standard mode | 4 | ||
| SCL clock frequency | fSCL | 400 | kHz | Fast mode | 4 | ||
| SCL clock frequency | fSCL | 3.4 | MHz | High-Speed mode, CB = 100 pF max | 4 | ||
| SCL clock frequency | fSCL | 1.7 | MHz | High-speed mode, CB = 400 pF max | 4 | ||
| Bus free time between STOP and START | tBUF | 4.7 | µs | Standard mode | 4 | ||
| Bus free time between STOP and START | tBUF | 1.3 | µs | Fast mode | 4 | ||
| Data setup time | tSU;tDAT | 250 | ns | Standard mode | 4 | ||
| Data setup time | tSU;tDAT | 100 | ns | Fast mode | 4 | ||
| Data setup time | tSU;tDAT | 10 | ns | High-speed mode | 4 | ||
| Capacitive load for SDA and SCL | CB | 400 | pF | 5 |
CAD (KiCad official)
- Symbol:
DAC5573IPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac5573ipwr-etched.step/dac5573ipwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac5573ipwr.step/dac5573ipwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
491d79e7622565e1, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).