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A96G174AEN
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ABOV Semicon Microcontrollers (MCU/MPU/SOC), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA96G174AEN
ABOV Semicon · Microcontrollers (MCU/MPU/SOC) · SOP-16
A96G174AEN from ABOV Semicon, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive logic supply pin for the device. |
| 2 | P00 | bidirectional | Port 0 bit 0 I/O with alternate functions SS, EC0, ADC input AN3 and the OCD DSDA data line, which has a pull-up. |
| 3 | P01 | bidirectional | Port 0 bit 1 I/O with alternate functions ADC input AN4, I2C data SDA and the OCD DSCL clock input, which has a pull-up. |
| 4 | P02 | bidirectional | Port 0 bit 2 I/O with alternate functions external interrupt EINT0 and I2C clock SCL; on the A96G174 this pin is also the RESETB reset input with pull-up. |
| 5 | P03 | bidirectional | Port 0 bit 3 I/O with alternate functions ADC input AN5, Timer 0 interval output T0O and Timer 0 PWM output PWM0O. |
| 6 | P04 | bidirectional | Port 0 bit 4 I/O with alternate functions ADC input AN6, Timer 2 interval output T2O and Timer 2 PWM output PWM2O. |
| 7 | P05 | bidirectional | Port 0 bit 5 I/O with alternate functions ADC input AN7 and USART external clock SCK. |
| 8 | P06 | bidirectional | Port 0 bit 6 I/O with alternate functions ADC input AN8, USART transmit or SPI MOSI (TXD) and Timer 1 complementary PWM output PWM1OB. |
| 9 | P13 | bidirectional | Port 1 bit 3 I/O with alternate functions ADC input AN11, external interrupt EINT1, Timer 1 event capture EC1 and USART clock XCK. |
| 10 | P14 | bidirectional | Port 1 bit 4 I/O with alternate functions ADC input AN12 and USART transmit or SPI MOSI (TXD). |
| 11 | P15 | bidirectional | Port 1 bit 5 I/O with alternate functions ADC input AN13, external interrupt EINT2 and USART receive or SPI MISO (RXD). |
| 12 | P16 | bidirectional | Port 1 bit 6 I/O with ADC input AN14; the RESETB reset function listed for this pin applies only to the A96S174. |
| 13 | P17 | bidirectional | Port 1 bit 7 I/O with alternate functions ADC input AN0 and Timer 1 PWM complementary output PWM1OB. |
| 14 | P20 | bidirectional | Port 2 bit 0 I/O with alternate functions ADC input AN1, Timer 1 interval output T1O and Timer 1 PWM output PWM1O. |
| 15 | P21 | bidirectional | Port 2 bit 1 I/O with ADC input AN2. |
| 16 | VSS | power_in | Ground reference pin for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ABOV Semicon |
| Package | SOP-16 |
| Category | Embedded Processors & Controllers |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | -0.3 | 6.5 | V | 61 | ||
| Voltage on any pin with respect to VSS | VI | -0.3 | V | Voltage on any pin with respect to VSS; max printed as VDD+0.3 | 61 | ||
| Maximum current output sourced by I/O pin | IOH | 10 | mA | Maximum current output sourced by (IOH per I/O pin) | 61 | ||
| Maximum current (sum IOH) | ∑IOH | 80 | mA | Maximum current (∑IOH) | 61 | ||
| Maximum current (IOL per I/O pin) | IOL | 80 | mA | Maximum current (IOL per I/O pin) | 61 | ||
| Maximum current (sum IOL) | ∑IOL | 100 | mA | Maximum current (∑IOL) | 61 | ||
| Total Power Dissipation | PT | 600 | mW | 61 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 61 | ||
| Operating Voltage | VDD | 1.8 | 5.5 | V | fX= 0.5 ~16MHz Internal RC | 61 | |
| Operating Temperature | TOPR | -40 | 85 | °C | VDD=1.8~5.5V | 61 | |
| Operating Temperature | TOPR | -40 | 105 | °C | 61 | ||
| Integral Linear Error | ILE | 4 | 8 | LSB | AVDD = 5.0V, MCLK = 8MHz | 62 | |
| Differential Linearity Error | DLE | 1 | 2 | LSB | 62 | ||
| Offset Error of Top | EOT | 4 | 8 | LSB | 62 | ||
| Offset Error of Bottom | EOB | 2 | 4 | LSB | 62 | ||
| Conversion Time | tCON | 7.5 | us | 12-bit resolution, 8MHz | 62 | ||
| Analog Input Leakage Current | IAN | 2 | uA | VDDREF=5.12V | 62 | ||
| ADC Operating Current (Enable) | IADC | 1 | 2 | mA | NOTE6 Enable VDD=5.12V | 62 | |
| ADC Operating Current (Disable) | IADC | 0.1 | uA | Disable | 62 | ||
| BGR Reference Voltage | VBGR | 1.164 | 1.2 | 1.236 | V | TA=+25°C | 63 |
| BGR Reference Voltage | VBGR | 1.146 | 1.2 | 1.254 | V | TA=-40°C ~ 85°C | 63 |
| BGR Reference Voltage | VBGR | 1.14 | 1.2 | 1.26 | V | TA=-40°C ~ 105°C | 63 |
| RESET Release Level | VPOR | 1.32 | V | NOTE | 63 | ||
| Minimum Pulse Width | tLW | 100 | us | NOTE | 63 | ||
| POR Current | IPOR | 0.2 | uA | NOTE | 63 | ||
| Detection Level | VLVR/VLVI | 1.61 | 1.75 | V | VLVR/VLVI can be measured when voltage drops (falling level). | 63 | |
| Detection Level | VLVR/VLVI | 1.63 | 1.77 | 1.91 | V | VLVR/VLVI can be measured when voltage drops (falling level). | 63 |
| Detection Level | VLVR/VLVI | 1.96 | 2.13 | 2.3 | V | VLVR/VLVI can be measured when voltage drops (falling level). | 63 |
| Detection Level | VLVR/VLVI | 2.26 | 2.46 | 2.66 | V | VLVR/VLVI can be measured when voltage drops (falling level). | 63 |
| Detection Level | VLVR/VLVI | 3.28 | 3.56 | 3.84 | V | VLVR/VLVI can be measured when voltage drops (falling level). | 63 |
| LVR and LVI Current (Enable Both) | IBL | 14 | 24 | uA | Enable (Both) VDD= 3V, RUN Mode | 63 | |
| LVR and LVI Current (Enable One of two) | IBL | 10 | 18 | uA | Enable (One of two) | 63 | |
| LVR and LVI Current (Disable Both) | IBL | 0.1 | uA | Disable (Both) VDD= 3V | 63 | ||
| Frequency | fIRC | 32 | MHz | VDD = 1.8, 5.5V | 64 | ||
| Tolerance | -1.5 | 1.5 | % | TA = 0°C to +50°C With 0.1uF Bypass capacitor | 64 | ||
| Tolerance | -2 | 2 | % | TA = -10°C to +70°C | 64 | ||
| Tolerance | -5 | 5 | % | TA = -40°C to +105°C | 64 | ||
| Clock Duty Ratio | TOD | 40 | 50 | 60 | % | 64 | |
| Stabilization Time | THFS | 100 | us | 64 | |||
| IRC Current Enable | IIRC | 0.2 | mA | Enable | 64 | ||
| IRC Current Disable | IIRC | 0.1 | uA | Disable | 64 | ||
| Frequency | fLSIRC | 102 | 128 | 154 | kHz | TA=-40°C ~ +85°C | 64 |
| Frequency | fLSIRC | 90 | 128 | 166 | kHz | TA=-40°C ~ +105°C | 64 |
| Stabilization Time | TLSIRC | 1 | ms | NOTE | 64 | ||
| LSIRC Current Enable | ILSIRC | 1 | uA | Enable | 64 | ||
| Output Low Voltage | VOL1 | 1 | V | VDD=4.5V, IOL= 10mA; All output ports except VOL2 | 65 | ||
| Input High Leakage Current | IIH | 1 | uA | All input ports | 65 | ||
| Input Low Leakage Current | IIL | -1 | uA | All input ports | 65 | ||
| Pull-Up Resistor RPU1 | RPU1 | 25 | 50 | 100 | kΩ | VI=0V, TA= 25°C, All Input ports, VDD=5.0V | 65 |
| Pull-Up Resistor RPU2 | RPU2 | 150 | 250 | 400 | kΩ | VI=0V, TA= 25°C, RESETB, VDD=5.0V | 65 |
| Supply Current IDD1 (RUN) | IDD1 | 0.7 | 2 | 4 | mA | fXIN= 16MHz, VDD= 5V | 65 |
| Supply Current IDD2 (IDLE) | IDD2 | 0.5 | 1.5 | 3 | mA | fXIN= 16MHz, VDD= 5V | 65 |
| Supply Current IDD3 (STOP) | IDD3 | 2 | 7 | uA | STOP @ WDT off & LVR off, VDD= 5.5V, TA= 25°C | 65 | |
| RESETB input low width | tRSL | 10 | us | Input, VDD= 5V | 66 | ||
| Interrupt input high, low width | tINTH | 200 | ns | All interrupt, VDD= 5V | 66 | ||
| Data Retention Supply Voltage | VDDDR | 1.8 | 5.5 | V | 71 | ||
| Data Retention Supply Current | IDDDR | 1 | uA | VDDR= 1.8V, (TA= 25°C), Stop mode | 71 | ||
| Endurance of Write/Erase | NFWE | 30000 | times | NOTE2 | 72 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | intended for simple implementation of look-up tables. A 16-bit base register (either the PC or | 26 |
CAD (KiCad official)
- Symbol:
A96G174AEN - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
a96g174aen-etched.step/a96g174aen-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a96g174aen.step/a96g174aen.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ABOV Semicon datasheet (106 pp, sha256
721ab8c941eedaf1, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).