AT45DB021E-SHN-B from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SI	input	Serial Input shifts in all command, address and data bits, latched on the rising edge of SCK and ignored while CS is deasserted.
2	SCK	input	Serial Clock controls data flow, with input latched on the rising edge and output SO data clocked out on the falling edge.
3	RESET	input	Active-low reset terminates the operation in progress and holds the internal state machine idle while low, and should be driven high externally if unused.
4	CS	input	Active-low Chip Select selects the device, requires a high-to-low transition to start and a low-to-high transition to end an operation, and a 10k Ohm pull-up to VCC is recommended.
5	WP	input	Active-low Write Protect protects all sectors set in the Sector Protection Register against program and erase, is internally pulled high, and should preferably be tied to VCC if unused.
6	VCC	power_in	Device power supply for a single 1.65 V to 3.6 V rail, where operation at invalid VCC voltages must not be attempted.
7	GND	power_in	Ground reference for the power supply, which must be connected to system ground.
8	SO	tri_state	Serial Output shifts data out on the falling edge of SCK and is in a high-impedance state whenever the device is deselected.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Memory
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ultra-Deep Power-Down Current	IUDPD		0.2	1	µA	CS = VCC. All other inputs at 0 V or VCC	47
Deep Power-Down Current	IDPD		4.5	12	µA	CS = VCC. All other inputs at 0 V or VCC	47
Standby Current	ISB		25	40	µA	CS = VCC. All other inputs at 0 V or VCC	47
Active Current, Low Power Read (01h) Operation	ICC1		6	9	mA	f = 1 MHz; IOUT = 0 mA	47
Active Current, Low Power Read (01h) Operation	ICC1		7	10	mA	f = 15 MHz; IOUT = 0 mA	47
Active Current, Read Operation	ICC2		10	12	mA	f = 50 MHz; IOUT = 0 mA	47
Active Current, Read Operation	ICC2		12	15	mA	f = 85 MHz; IOUT = 0 mA	47
Active Current, Program Operation	ICC3		10	12	mA	CS = VCC	47
Active Current, Erase Operation	ICC4		8	12	mA	CS = VCC	47
Input Load Current	ILI			1	µA	All inputs at CMOS levels	47
Output Leakage Current	ILO			1	µA	All inputs at CMOS levels	47
Output Low Voltage	VOL			0.2	V	IOL = 100µA	47
Absolute maximum temperature under bias		-55		125	°C	Temperature under Bias	47
Absolute maximum storage temperature		-65		150	°C	Storage Temperature	47
Absolute maximum input voltage		-0.6		6.25	V	All input voltages (except VCC but including NC pins) with respect to ground	47
Operating Temperature (Case)		-40		85	°C	Industrial	47
VCC Power Supply	VCC	1.65		3.6	V		47
SCK Frequency	fSCK			70	MHz		48
SCK Frequency for Continuous Read	fCAR1			70	MHz		48
SCK Frequency for Continuous Read (Low Frequency)	fCAR2			33	MHz		48
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode)	fCAR3			15	MHz		48
SCK High Time	tWH	4			ns		48
SCK Low Time	tWL	4			ns		48
SCK Rise Time, Peak-to-peak	tSCKR			0.1	V/ns		48
SCK Fall Time, Peak-to-peak	tSCKF			0.1	V/ns		48
Minimum CS High Time	tCS	20			ns		48
CS Setup Time	tCSS	6			ns		48
CS Hold Time	tCSH	5			ns		48
Data In Setup Time	tSU	2			ns		48
Data In Hold Time	tH	1			ns		48
Output Hold Time	tHO	0			ns		48
Output Disable Time	tDIS			8	ns		48
Output Valid	tV			7	ns		48
WP Low to Protection Enabled	tWPE			1	µs		48
WP High to Protection Disabled	tWPD			1	µs		48
Freeze Sector Lockdown Time (from CS High)	tLOCK			200	µs		48
CS High to Ultra-Deep Power-Down	tEUDPD			3	µs		48
Minimum CS Low Time to Exit Ultra-Deep Power-Down	tCSLU	20			ns		48
Exit Ultra-Deep Power-Down Time	tXUDPD			120	µs		48
CS High to Deep Power-Down	tEDPD			2	µs		48
Resume from Deep Power-Down Time	tRDPD			35	µs		48
Page to Buffer Transfer Time	tXFR			100	µs		48
Page to Buffer Compare Time	tCOMP			100	µs		48
RESET Pulse Width	tRST	10			µs		48
RESET Recovery Time	tREC	1			µs		48
Software Reset Time	tSWRST			35	µs		48
Page Erase and Programming Time (256/264 bytes)	tEP		10	35	ms		49
Page Programming Time	tP		1.5	3	ms		49
Byte Programming Time	tBP		8		µs		49
Page Erase Time	tPE		6	25	ms		49
Block Erase Time	tBE		25	35	ms		49
Sector Erase Time	tSE		350	550	ms		49
Chip Erase Time	tCE		3	4	s		49
OTP Security Register Program Time	tOTPP		200	500	µs		49

CAD (KiCad official)

Symbol: AT45DB021E-SHN-B
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: at45db021e-shn-b-etched.step / at45db021e-shn-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db021e-shn-b.step / at45db021e-shn-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (70 pp, sha256 e0494e3584e1a84f, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AT45DB021E-SHN-B

Verified AT45DB021E-SHN-B

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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