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SST26VF032BT-104I

Public Made by Adom

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Microchip Tech NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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SST26VF032BT-104I

Microchip Tech · NOR FLASH · SOIC-8-208mil

SST26VF032BT-104I from Microchip Tech, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input The device is enabled by a high to low transition on CE#, and CE# must remain low for the duration of any command sequence or the command/data input sequence of a write operation.
2 SO/SIO1 bidirectional In SPI mode (default after power-on) SO transfers data out of the device on the falling edge of SCK, and it becomes SIO1 for Quad I/O mode when the EQIO command is executed.
3 WP#/SIO2 bidirectional WP# is used with the WPEN and IOC bits to prohibit writes to the Block-Protection register, works only in SPI single-bit and dual-bit read mode, and becomes SIO2 in Quad I/O mode.
4 VSS power_in Ground reference for the device.
5 SI/SIO0 bidirectional In SPI mode (default after power-on) SI latches commands, addresses, or data on the rising edge of SCK, and it becomes SIO0 for Quad I/O mode when the EQIO command is executed.
6 SCK input Serial clock that latches commands, addresses, or input data on its rising edge and shifts output data out on its falling edge.
7 HOLD#/SIO3 bidirectional HOLD# temporarily stops serial communication while the device is selected, must be tied high when not in use, works only in SPI single-bit and dual-bit read mode, and becomes SIO3 in Quad I/O mode.
8 VDD power_in Power supply pin; the datasheet specifies a single 2.3-3.6V supply for write operations and 2.7-3.6V or 2.3-3.6V for read operations.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage (operating range) VDD 2.3 3.6 V 42
Ambient temperature, Industrial TA -40 85 °C Industrial range 42
Temperature under bias -55 125 °C 42
Storage temperature -65 150 °C 42
Package power dissipation capability 1 W TA = 25°C 42
Surface mount solder reflow temperature 260 °C 10 seconds 42
Output short circuit current 50 mA Output shorted for no more than one second; no more than one output shorted at a time 42
VDD min to read operation TPU-READ 100 µs 42
VDD min to write operation TPU-WRITE 100 µs 42
Power-down duration TPD 100 ms 42
VDD off time VOFF 0.3 V 0V recommended 42
Read current (40 MHz) IDDR1 8 15 mA VDD=VDD Max, CE#=0.1 VDD/0.9 VDD@40 MHz, SO=open 44
Read current (104 MHz) IDDR2 20 mA VDD = VDD Max, CE#=0.1 VDD/0.9 VDD@104 MHz, SO=open 44
Program and erase current IDDW 25 mA CE#=VDD Max 44
Standby current ISB 15 45 µA CE#=VDD, VIN=VDD or VSS 44
Input leakage current ILI 2 µA VIN=GND to VDD, VDD=VDD Max 44
Output leakage current ILO 2 µA VOUT=GND to VDD, VDD=VDD Max 44
Input low voltage VIL 0.8 V VDD=VDD Min 44
Output low voltage VOL 0.2 V IOL=100 µA, VDD=VDD Min 44
Output pin capacitance COUT 8 pF VOUT = 0V 44
Input capacitance CIN 6 pF VIN = 0V 44
Endurance NEND 100000 Cycles JEDEC Standard A117 44
Data retention TDR 100 Years JEDEC Standard A103 44
Sector-erase time TSE 25 ms 44
Block-erase time TBE 25 ms 44
Chip-erase time TSCE 50 ms 44
Page-program time TPP 1.5 ms 44
Program security-ID time TPSID 1.5 ms 44
Write-suspend latency TWS 25 µs 44
Write-protection enable bit latency TWpen 25 ms 44
Serial clock frequency FCLK 104 MHz Limits - 104 MHz 45
Serial clock period TCLK 9.6 ns Limits - 104 MHz 45
Serial clock high time TSCKH 4.5 ns Limits - 104 MHz 45
Serial clock low time TSCKL 4.5 ns Limits - 104 MHz 45
Serial clock rise time (slew rate) TSCKR 0.1 V/ns Limits - 104 MHz 45
Serial clock fall time (slew rate) TSCKF 0.1 V/ns Limits - 104 MHz 45
CE# active setup time TCES 5 ns Limits - 104 MHz 45
CE# active hold time TCEH 5 ns Limits - 104 MHz 45
CE# not active setup time TCHS 5 ns Limits - 104 MHz 45
CE# not active hold time TCHH 5 ns Limits - 104 MHz 45
CE# high time TCPH 12 ns Limits - 104 MHz 45
CE# high to high-Z output TCHZ 12 ns Limits - 104 MHz 45
SCK low to low-Z output TCLZ 0 ns Limits - 104 MHz 45
HOLD# low setup time THLS 5 ns Limits - 104 MHz 45
HOLD# high setup time THHS 5 ns Limits - 104 MHz 45
HOLD# low hold time THLH 5 ns Limits - 104 MHz 45
HOLD# high hold time THHH 5 ns Limits - 104 MHz 45
Data in setup time TDS 3 ns Limits - 104 MHz 45
Data in hold time TDH 4 ns Limits - 104 MHz 45
Output hold from SCK change TOH 0 ns Limits - 104 MHz 45
Reset to read (non-data operation) TR(o) 20 ns 46
Reset recovery from program or suspend TR(p) 100 µs 46
Reset recovery from erase TR(e) 1 ms 46

CAD (KiCad official)

  • Symbol: SST26VF032BT-104I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
  • 3D model files: sst26vf032bt-104i-etched.step / sst26vf032bt-104i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sst26vf032bt-104i.step / sst26vf032bt-104i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (77 pp, sha256 d42f884a5764dfad, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF