DP83TG720RWRHARQ1 from Texas Instruments, in a TQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MDC	input	Management data clock input that synchronizes MDIO serial management data; it may be stopped by the external management entity when the bus is idle.
2	INT_N	output	Active-low open-drain interrupt output with a weak internal pull-up (9 kΩ typical); it is asserted low on an interrupt and must be cleared through registers.
3	RESET_N	input	Active-low reset input with internal 9 kΩ pull-up; it must be held low for at least 10 µs to force a reset, and bootstrap pins are re-sampled on release.
4	XO	output	Crystal reference clock output used only with a crystal; it must be left unconnected when a CMOS-level oscillator drives XI.
5	XI	input	Reference clock input accepting a 25 MHz ±100 ppm crystal or oscillator, or a CMOS-level oscillator driving XI alone.
6	LED_1/GPIO_1	bidirectional	LED_1 indicates link status and flashes for TX/RX activity; it can also function as GPIO_1 and has an internal 9 kΩ pull-down.
7	VSLEEP	power_in	Sleep-domain supply of 3.3 V (2.97 V to 3.63 V); if sleep is not used it must be connected to VDDA3P3.
8	WAKE	input	Active-high wake input in the VSLEEP domain with a 50 kΩ internal pull-down; a high pulse wakes the PHY from sleep, and it may be tied to VSLEEP if sleep is unused.
9	VDD1P0	power_in	1.0 V core supply (0.95 V to 1.1 V) that requires the recommended decoupling network.
10	INH	output	Active-high PMOS open-drain output that releases the line in sleep so an external 10 kΩ pull-down can work, and otherwise drives high to VSLEEP.
11	VDDA3P3	power_in	3.3 V analog/core supply (2.97 V to 3.63 V) that requires the recommended decoupling network.
12	TRD_P	bidirectional	Positive side of the differential MDI pair for 1000BASE-T1 operation per IEEE 802.3bp; absolute maximum is -0.5 V to 4 V.
13	TRD_M	bidirectional	Negative side of the differential MDI pair for 1000BASE-T1 operation per IEEE 802.3bp; absolute maximum is -0.5 V to 4 V.
14	STRP_1	input	Strap input used to set the PHY_AD address bit, sampled at power-up and reset and carrying a 6.3 kΩ internal pull-down.
15	RX_CTRL	output	RGMII receive control output combining RX_DV (valid on RX_CLK rising edge) and RX_ER (on RX_CLK falling edge); it is also a strap pin with a 6.3 kΩ internal pull-down.
16	CLKOUT/GPIO_2	bidirectional	Clock output that defaults to a buffered 25 MHz copy of XI; it can be disabled by writing register 0x0453 = 0x0006 or used as GPIO_2.
17	DNC	unconnected	Do not connect; test structures tied to these pins must be left floating to avoid damage or entering an incorrect PHY mode.
18	DNC	unconnected	Do not connect; test structures tied to these pins must be left floating to avoid damage or entering an incorrect PHY mode.
19	DNC	unconnected	Do not connect; test structures tied to these pins must be left floating to avoid damage or entering an incorrect PHY mode.
20	DNC	unconnected	Do not connect; test structures tied to these pins must be left floating to avoid damage or entering an incorrect PHY mode.
21	VDD1P0	power_in	1.0 V core supply (0.95 V to 1.1 V) that requires the recommended decoupling network.
22	VDDIO	power_in	I/O supply that operates at 1.8 V (1.62 V to 1.98 V), 2.5 V (2.25 V to 2.75 V), or 3.3 V (2.97 V to 3.63 V).
23	RX_D3	output	RGMII receive data bit 3, driven synchronously with RX_CLK and valid when RX_DV is set; it has an internal 9 kΩ pull-down and a status-bit role in in-band signaling.
24	RX_D2	output	RGMII receive data bit 2, driven synchronously with RX_CLK and valid when RX_DV is set; it has an internal 9 kΩ pull-down.
25	RX_D1	output	RGMII receive data bit 1, driven synchronously with RX_CLK and valid when RX_DV is set; it has an internal 9 kΩ pull-down.
26	RX_D0	output	RGMII receive data bit 0, driven synchronously with RX_CLK and valid when RX_DV is set; it has an internal 9 kΩ pull-down.
27	RX_CLK	output	RGMII receive clock output that provides the 125 MHz clock to the MAC in RGMII mode.
28	TX_CLK	input	RGMII transmit clock input that the MAC provides as a 125 MHz clock to the PHY in RGMII mode.
29	TX_CTRL	input	RGMII transmit control input combining TX_EN (before the TX_CLK rising edge) and TX_ER (at the TX_CLK falling edge) from the MAC.
30	TX_D3	input	RGMII transmit data bit 3 received from the MAC, forming the TX_D[3:0] nibble.
31	TX_D2	input	RGMII transmit data bit 2 received from the MAC, forming the TX_D[3:0] nibble.
32	TX_D1	input	RGMII transmit data bit 1 received from the MAC, forming the TX_D[3:0] nibble.
33	TX_D0	input	RGMII transmit data bit 0 received from the MAC, forming the TX_D[3:0] nibble.
34	VDDIO	power_in	I/O supply that operates at 1.8 V (1.62 V to 1.98 V), 2.5 V (2.25 V to 2.75 V), or 3.3 V (2.97 V to 3.63 V) and requires the recommended decoupling network.
35	LED_0/GPIO_0	bidirectional	LED_0 indicates link status and also sets the MDI master/slave strap at boot, with an internal 9 kΩ pull-down that defaults the PHY to slave mode.
36	MDIO	bidirectional	Open-drain management data input/output shared with the management station; it requires an external pull-up (2.2 kΩ recommended).
37	GND	power_in	Ground connection on the exposed die-attach pad (DAP), which must be soldered to the PCB for thermal and mechanical performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFN-36-EP(6x6)
Category	Communication Interface Chip/UART/485/232
Pins	37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDDA3P3	VDDA3P3	-0.5		4	V		9
Supply voltage VDD1P0	VDD1P0	-0.5		1.4	V		9
Supply voltage VDDIO (3.3V)	VDDIO	-0.5		4	V		9
Supply voltage VDDIO (2.5V)	VDDIO	-0.5		2.9	V		9
Supply voltage VDDIO (1.8V)	VDDIO	-0.5		2.2	V		9
Supply voltage VSLEEP	VSLEEP	-0.5		4	V		9
MDI pins TRD_M, TRD_P voltage		-0.5		4	V		9
LVCMOS/LVTTL input voltage (MDC, RESET, XI, RX/TX pins, LED, MDIO and others)		-0.5			V		9
LVCMOS/LVTTL input voltage, WAKE		-0.5			V		9
LVCMOS/LVTTL output voltage (INT, LED_1, RX_CTRL, CLKOUT, RX_D[3:0], RX_CLK, LED_0, MDIO)		-0.5			V		9
LVCMOS/LVTTL output voltage, INH		-0.5			V		9
Junction temperature	TJ			150	°C		9
Storage temperature	Tstg	-65		150	°C		9
I/O supply voltage, 1.8 V operation	VDDIO	1.62	1.8	1.98	V		9
I/O supply voltage, 2.5 V operation	VDDIO	2.25	2.5	2.75	V		9
I/O supply voltage, 3.3 V operation	VDDIO	2.97	3.3	3.63	V		9
Core supply voltage, 3.3 V	VDDA3P3	2.97	3.3	3.63	V		9
Core supply voltage, 1.0 V	VDD1P0	0.95	1	1.1	V		9
Sleep supply voltage, 3.3 V	VSLEEP	2.97	3.3	3.63	V		9
Ambient operating temperature	TA	-40		125	°C		10
XI input high-level voltage	VIH	1.3			V		10
XI input low-level voltage	VIL			0.5	V		10
WAKE pin input high-level voltage	VIH	2			V	VSLEEP = 3.3V ± 10%	10
WAKE pin input low-level voltage	VIL			0.8	V	VSLEEP = 3.3V ± 10%	10
INH pin output high-level voltage	VOH	2.4			V	IOH = -2mA, VSLEEP = 3.3V ± 10%	10
Output high-level voltage (3.3V VDDIO I/O)	VOH	2.4			V	IOH = -2mA, VDDIO = 3.3V ± 10%	10
Output low-level voltage (3.3V VDDIO I/O)	VOL			0.4	V	IOL = 2mA, VDDIO = 3.3V ± 10%	10
Input high-level voltage (3.3V VDDIO I/O)	VIH	2			V	VDDIO = 3.3V ± 10%	10
Input low-level voltage (3.3V VDDIO I/O)	VIL			0.8	V	VDDIO = 3.3V ± 10%	10
Output high-level voltage (2.5V VDDIO I/O)	VOH	2			V	IOH = -2mA, VDDIO = 2.5V ± 10%	10
Output low-level voltage (2.5V VDDIO I/O)	VOL			0.4	V	IOL = 2mA, VDDIO = 2.5V ± 10%	10
Input high-level voltage (2.5V VDDIO I/O)	VIH	1.7			V	VDDIO = 2.5V ± 10%	10
Input low-level voltage (2.5V VDDIO I/O)	VIL			0.7	V	VDDIO = 2.5V ± 10%	10
Output low-level voltage (1.8V VDDIO I/O)	VOL			0.45	V	IOL = 2mA, VDDIO = 1.8V ± 10%	10
High input current (MDIO)	IIH	-5		5	µA	VIN = VCC, -40°C to 125°C	11
High input current (RGMII input pins, MDC)	IIH	-20		20	µA	VIN = VCC, -40°C to 125°C	11
High-impedance input current (MDIO)	IOZ	-40		40	µA	VIN swept 0V to VCC, -40°C to 125°C	11
Input low current (RGMII input pins, MDC, MDIO)	IIL	-40		5	µA	VIN = GND, -40°C to 125°C	11
Tri-state output current (LED_1, RX_D[3:0], RX_CLK, LED_0)	IOZ	-40		10	µA	VIN swept 0V to VCC, -40°C to 125°C	11
Tri-state output current (STRP_1, RX_CTRL)	IOZ	-60		60	µA	VIN swept 0V to VCC, -40°C to 125°C	11
Integrated pull-up resistance (INT, RESET)	Rpull-up	6.5	9	12.5	kΩ		11
Integrated pull-down resistance (STRP_1, RX_CTRL)	Rpull-down	4.725	6.3	7.875	kΩ		11
Integrated pull-down resistance (LED_1, RX_D[3:0], RX_CLK, LED_0)	Rpull-down	7.3	9	13	kΩ		11
Integrated resistance, WAKE pin		35	50	62.5	kΩ		11
Integrated MAC series termination resistor (default)	Rseries	24	42	52	Ω	Default; RX_D[3:0], RX_CTRL and RX_CLK	11
Integrated MAC series termination resistor (register 0x0456 = 0x0148)	Rseries	30	52	65	Ω	RX_D[3:0], RX_CTRL and RX_CLK	11
Integrated MAC series termination resistor (register 0x0456 = 0x0168)	Rseries	40	70	84	Ω	RX_D[3:0], RX_CTRL and RX_CLK	11
Sleep supply current, VSLEEP	ISLEEP		485	840	µA	Sleep mode	11
IO supply current, VDDIO = 1.8V (standby)	IDDIO		4	11	mA	Standby	11
IO supply current, VDDIO = 2.5V (standby)	IDDIO		6	13	mA	Standby	11
IO supply current, VDDIO = 3.3V (standby)	IDDIO		8	15	mA	Standby	11
Core supply current, 3.3V (standby)	IDDA3P3		16	18	mA	Standby	11
Core supply current, 1.0V (standby)	IDD1P0		33	112	mA	Standby	11
IO supply current, VDDIO = 1.8V (operating, RGMII)	IDDIO		20	25	mA	Operating, RGMII; voltage ±10%, traffic 100%, packet size 1518, random content	11
IO supply current, VDDIO = 2.5V (operating, RGMII)	IDDIO		26	30	mA	Operating, RGMII; voltage ±10%, traffic 100%, packet size 1518, random content	11
IO supply current, VDDIO = 3.3V (operating, RGMII)	IDDIO		33	40	mA	Operating, RGMII; voltage ±10%, traffic 100%, packet size 1518, random content	12
Core supply current, 3.3V (operating, RGMII)	IDDA3P3		85	89	mA	Operating, RGMII; voltage ±10%, traffic 100%, packet size 1518, random content	12
Core supply current, 1.0V (operating, RGMII)	IDD1P0		177	250	mA	Operating, RGMII; voltage ±10%, traffic 100%, packet size 1518, random content	12
Sleep supply current, VSLEEP	ISLEEP		1000	1500	µA	VSLEEP = 3.3V ± 10%	12
Junction-to-ambient thermal resistance	RθJA		32.5		°C/W		10

CAD (KiCad official)

Symbol: DP83TG720RWRHARQ1
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: TQFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: dp83tg720rwrharq1-etched.step / dp83tg720rwrharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tg720rwrharq1.step / dp83tg720rwrharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (218 pp, sha256 1a3eac675e416d69, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DP83TG720RWRHARQ1

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