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STM32F732VET6

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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Contents

README

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STM32F732VET6

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

STM32F732VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2 and FMC_A23.
2 PE3 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED0, SAI1_SD_B and FMC_A19.
3 PE4 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED1, SPI4_NSS, SAI1_FS_A and FMC_A20.
4 PE5 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A and FMC_A21.
5 PE6 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCK_B and FMC_A22.
6 VBAT power_in Backup power supply for the RTC, the 32x32-bit backup registers and the 4 Kbytes of backup SRAM.
7 PC13 bidirectional Backup-domain GPIO (FT) supplied through a power switch that sinks at most 3 mA, so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source; additional functions RTC_TAMP1/RTC_TS/RTC_OUT and WKUP4.
8 PC14-OSC32_IN bidirectional Backup-domain GPIO (FT) with the same power-switch limits as PC13 (3 mA, 2 MHz at 30 pF, no current sourcing), serving as the OSC32_IN oscillator input when oscillator mode is selected.
9 PC15-OSC32_OUT bidirectional Backup-domain GPIO (FT) with the same power-switch limits as PC13 (3 mA, 2 MHz at 30 pF, no current sourcing), serving as the OSC32_OUT oscillator output when oscillator mode is selected.
10 VSS power_in Ground pin; all voltages are referenced to VSS.
11 VDD power_in Application supply pin for I/Os and the internal regulator, specified for 1.7 V to 3.6 V.
12 PH0-OSC_IN bidirectional GPIO (FT, 5 V tolerant except in oscillator mode) used as the HSE oscillator input OSC_IN.
13 PH1-OSC_OUT bidirectional GPIO (FT, 5 V tolerant except in oscillator mode) used as the HSE oscillator output OSC_OUT.
14 NRST bidirectional Bidirectional reset pin with weak pull-up resistor.
15 PC0 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SAI2_FS_B, OTG_HS_ULPI_STP and FMC_SDNWE; additional functions ADC1_IN10, ADC2_IN10 and ADC3_IN10.
16 PC1 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED0, SPI2_MOSI/I2S2_SD and SAI1_SD_A; additional functions ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3 and WKUP3.
17 PC2 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI2_MISO, OTG_HS_ULPI_DIR and FMC_SDNE0; additional functions ADC1_IN12, ADC2_IN12 and ADC3_IN12.
18 PC3 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT and FMC_SDCKE0; additional functions ADC1_IN13, ADC2_IN13 and ADC3_IN13.
19 VSSA power_in Dedicated analog ground pin for the ADC and DAC domain.
20 VREF+ power_in Positive reference voltage pin for the ADC and DAC.
21 VDDA power_in Dedicated analog supply pin for the ADC and DAC domain.
22 PA0-WKUP bidirectional Analog-capable GPIO (FT) with alternate functions TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and SAI2_SD_B, additional functions ADC1_IN0, ADC2_IN0, ADC3_IN0 and WKUP1; if BYPASS_REG is tied to VDD (regulator OFF/internal reset ON) it is used as an active-low internal reset.
23 PA1 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3 and SAI2_MCK_B; additional functions ADC1_IN1, ADC2_IN1 and ADC3_IN1.
24 PA2 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX and SAI2_SCK_B; additional functions ADC1_IN2, ADC2_IN2, ADC3_IN2 and WKUP2.
25 PA3 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX and OTG_HS_ULPI_D0; additional functions ADC1_IN3, ADC2_IN3 and ADC3_IN3.
26 VSS power_in Ground pin; all voltages are referenced to VSS.
27 VDD power_in Application supply pin for I/Os and the internal regulator, specified for 1.7 V to 3.6 V.
28 PA4 bidirectional 3.3 V-tolerant I/O (TTa) connected directly to the ADC, with alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK and OTG_HS_SOF; additional functions ADC1_IN4, ADC2_IN4 and DAC_OUT1.
29 PA5 bidirectional 3.3 V-tolerant I/O (TTa) connected directly to the ADC, with alternate functions TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK and OTG_HS_ULPI_CK; additional functions ADC1_IN5, ADC2_IN5 and DAC_OUT2.
30 PA6 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO and TIM13_CH1; additional functions ADC1_IN6 and ADC2_IN6.
31 PA7 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1 and FMC_SDNWE; additional functions ADC1_IN7 and ADC2_IN7.
32 PC4 bidirectional 5 V-tolerant GPIO (FT) with alternate functions I2S1_MCK and FMC_SDNE0; additional functions ADC1_IN14 and ADC2_IN14.
33 PC5 bidirectional 5 V-tolerant GPIO (FT) with alternate function FMC_SDCKE0; additional functions ADC1_IN15 and ADC2_IN15.
34 PB0 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS and OTG_HS_ULPI_D1; additional functions ADC1_IN8 and ADC2_IN8.
35 PB1 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N and OTG_HS_ULPI_D2; additional functions ADC1_IN9 and ADC2_IN9.
36 PB2 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SAI1_SD_A, SPI3_MOSI/I2S3_SD and QUADSPI_CLK.
37 PE7 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_ETR, UART7_Rx, QUADSPI_BK2_IO0 and FMC_D4.
38 PE8 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH1N, UART7_Tx, QUADSPI_BK2_IO1 and FMC_D5.
39 PE9 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH1, UART7_RTS, QUADSPI_BK2_IO2 and FMC_D6.
40 PE10 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH2N, UART7_CTS, QUADSPI_BK2_IO3 and FMC_D7.
41 PE11 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH2, SPI4_NSS, SAI2_SD_B and FMC_D8.
42 PE12 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH3N, SPI4_SCK, SAI2_SCK_B and FMC_D9.
43 PE13 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH3, SPI4_MISO, SAI2_FS_B and FMC_D10.
44 PE14 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH4, SPI4_MOSI, SAI2_MCK_B and FMC_D11.
45 PE15 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_BKIN and FMC_D12.
46 PB10 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf, 20 mA drive in Fm+) with alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX and OTG_HS_ULPI_D3.
47 PB11 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf, 20 mA drive in Fm+) with alternate functions TIM2_CH4, I2C2_SDA, USART3_RX and OTG_HS_ULPI_D4.
48 VCAP_1 power_in Output of the internal voltage regulator; must be connected to an external capacitor as specified in section 6.3.2.
49 VSS power_in Ground pin; all voltages are referenced to VSS.
50 VDD power_in Application supply pin for I/Os and the internal regulator, specified for 1.7 V to 3.6 V.
51 PB12 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, OTG_HS_ULPI_D5 and OTG_HS_ID.
52 PB13 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS and OTG_HS_ULPI_D6; additional function OTG_HS_VBUS.
53 PB14 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, SDMMC2_D0 and OTG_HS_DM.
54 PB15 bidirectional 5 V-tolerant GPIO (FT) with alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, SDMMC2_D1 and OTG_HS_DP.
55 PD8 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART3_TX and FMC_D13.
56 PD9 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART3_RX and FMC_D14.
57 PD10 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART3_CK and FMC_D15.
58 PD11 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A and FMC_A16/FMC_CLE.
59 PD12 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM4_CH1, LPTIM1_IN1, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A and FMC_A17/FMC_ALE.
60 PD13 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM4_CH2, LPTIM1_OUT, QUADSPI_BK1_IO3, SAI2_SCK_A and FMC_A18.
61 PD14 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM4_CH3, UART8_CTS and FMC_D0.
62 PD15 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM4_CH4, UART8_RTS and FMC_D1.
63 PC6 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC2_D6 and SDMMC1_D6.
64 PC7 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC2_D7 and SDMMC1_D7.
65 PC8 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK and SDMMC1_D0.
66 PC9 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0 and SDMMC1_D1.
67 PA8 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK and OTG_FS_SOF.
68 PA9 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK and USART1_TX; additional function OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH3, USART1_RX and OTG_FS_ID.
70 PA11 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_CH4, USART1_CTS, CAN1_RX and OTG_FS_DM.
71 PA12 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX and OTG_FS_DP.
72 PA13 bidirectional 5 V-tolerant GPIO (FT) which after reset is the JTMS-SWDIO serial-wire debug data pin.
73 VCAP_2 power_in Output of the internal voltage regulator; must be connected to an external capacitor as specified in section 6.3.2.
74 VSS power_in Ground pin; all voltages are referenced to VSS.
75 VDD power_in Application supply pin for I/Os and the internal regulator, specified for 1.7 V to 3.6 V.
76 PA14 bidirectional 5 V-tolerant GPIO (FT) which after reset is the JTCK-SWCLK serial-wire debug clock pin.
77 PA15 bidirectional 5 V-tolerant GPIO (FT) with JTDI after reset and alternate functions TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS and UART4_RTS.
78 PC10 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1 and SDMMC1_D2.
79 PC11 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS and SDMMC1_D3.
80 PC12 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX and SDMMC1_CK.
81 PD0 bidirectional 5 V-tolerant GPIO (FT) with alternate functions CAN1_RX and FMC_D2.
82 PD1 bidirectional 5 V-tolerant GPIO (FT) with alternate functions CAN1_TX and FMC_D3.
83 PD2 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TRACED2, TIM3_ETR, UART5_RX and SDMMC1_CMD.
84 PD3 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI2_SCK/I2S2_CK, USART2_CTS and FMC_CLK.
85 PD4 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART2_RTS and FMC_NOE.
86 PD5 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART2_TX and FMC_NWE.
87 PD6 bidirectional 5 V-tolerant GPIO (FT) with alternate functions SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, SDMMC2_CK and FMC_NWAIT.
88 PD7 bidirectional 5 V-tolerant GPIO (FT) with alternate functions USART2_CK, SDMMC2_CMD and FMC_NE1.
89 PB3 bidirectional 5 V-tolerant GPIO (FT) with JTDO/TRACESWO after reset and alternate functions TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SDMMC2_D2.
90 PB4 bidirectional 5 V-tolerant GPIO (FT) with NJTRST after reset and alternate functions TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS and SDMMC2_D3.
91 PB5 bidirectional 5 V-tolerant GPIO (FT, note 4) with alternate functions TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, OTG_HS_ULPI_D7 and FMC_SDCKE1.
92 PB6 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions TIM4_CH1, I2C1_SCL, USART1_TX, QUADSPI_BK1_NCS and FMC_SDNE1.
93 PB7 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions TIM4_CH2, I2C1_SDA, USART1_RX and FMC_NL.
94 BOOT0 input Dedicated BOOT0 boot-mode selection pin, also used as VPP for Flash programming with VPP.
95 PB8 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDMMC2_D4 and SDMMC1_D4.
96 PB9 bidirectional 5 V-tolerant GPIO with I2C Fm+ option (FTf) with alternate functions TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDMMC2_D5 and SDMMC1_D5.
97 PE0 bidirectional 5 V-tolerant GPIO (FT) with alternate functions TIM4_ETR, LPTIM1_ETR, UART8_Rx, SAI2_MCK_A and FMC_NBL0.
98 PE1 bidirectional 5 V-tolerant GPIO (FT) with alternate functions LPTIM1_IN2, UART8_Tx and FMC_NBL1.
99 VSS power_in Ground pin; all voltages are referenced to VSS.
100 VDD power_in Application supply pin for I/Os and the internal regulator, specified for 1.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

CAD (KiCad official)

  • Symbol: STM32F732VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f732vet6-etched.step / stm32f732vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f732vet6.step / stm32f732vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (228 pp, sha256 33237d71f4a80d09, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF