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TUSB8041RGCT

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Texas Instruments USB ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tusb8041rgctfactory-2.0.0extractor-text
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TUSB8041RGCT

Texas Instruments · USB ICs · VQFN-64-EP(9x9)

TUSB8041RGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB_DP_DN1 bidirectional USB High-speed differential transceiver (positive) for downstream Port 1.
2 USB_DM_DN1 bidirectional USB High-speed differential transceiver (negative) for downstream Port 1.
3 USB_SSTXP_DN1 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 1.
4 USB_SSTXM_DN1 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 1.
5 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
6 USB_SSRXP_DN1 input USB SuperSpeed receiver differential pair (positive) for downstream Port 1.
7 USB_SSRXM_DN1 input USB SuperSpeed receiver differential pair (negative) for downstream Port 1.
8 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
9 USB_DP_DN2 bidirectional USB High-speed differential transceiver (positive) for downstream Port 2.
10 USB_DM_DN2 bidirectional USB High-speed differential transceiver (negative) for downstream Port 2.
11 USB_SSTXP_DN2 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 2.
12 USB_SSTXM_DN2 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 2.
13 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
14 USB_SSRXP_DN2 input USB SuperSpeed receiver differential pair (positive) for downstream Port 2.
15 USB_SSRXM_DN2 input USB SuperSpeed receiver differential pair (negative) for downstream Port 2.
16 VDD33 power_in 3.3-V power rail; recommended supply range is 3.0 V to 3.6 V (3.3 V nominal).
17 USB_DP_DN3 bidirectional USB High-speed differential transceiver (positive) for downstream Port 3.
18 USB_DM_DN3 bidirectional USB High-speed differential transceiver (negative) for downstream Port 3.
19 USB_SSTXP_DN3 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 3.
20 USB_SSTXM_DN3 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 3.
21 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
22 USB_SSRXP_DN3 input USB SuperSpeed receiver differential pair (positive) for downstream Port 3.
23 USB_SSRXM_DN3 input USB SuperSpeed receiver differential pair (negative) for downstream Port 3.
24 USB_DP_DN4 bidirectional USB High-speed differential transceiver (positive) for downstream Port 4.
25 USB_DM_DN4 bidirectional USB High-speed differential transceiver (negative) for downstream Port 4.
26 USB_SSTXP_DN4 output USB SuperSpeed transmitter differential pair (positive) for downstream Port 4.
27 USB_SSTXM_DN4 output USB SuperSpeed transmitter differential pair (negative) for downstream Port 4.
28 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
29 USB_SSRXP_DN4 input USB SuperSpeed receiver differential pair (positive) for downstream Port 4.
30 USB_SSRXM_DN4 input USB SuperSpeed receiver differential pair (negative) for downstream Port 4.
31 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
32 PWRCTL4/BATEN4 bidirectional USB Port 4 power-on control for downstream power switch and battery charging enable; the value sampled at reset de-assertion sets Port 4 battery charging support (0 = not supported, 1 = supported).
33 PWRCTL3/BATEN3 bidirectional USB Port 3 power-on control for downstream power switch and battery charging enable; the value sampled at reset de-assertion sets Port 3 battery charging support (0 = not supported, 1 = supported).
34 VDD33 power_in 3.3-V power rail; recommended supply range is 3.0 V to 3.6 V (3.3 V nominal).
35 PWRCTL2/BATEN2 bidirectional USB Port 2 power-on control for downstream power switch and battery charging enable; the value sampled at reset de-assertion sets Port 2 battery charging support (0 = not supported, 1 = supported).
36 PWRCTL1/BATEN1 bidirectional USB Port 1 power-on control for downstream power switch and battery charging enable; the value sampled at reset de-assertion sets Port 1 battery charging support (0 = not supported, 1 = supported).
37 SDA/SMBDAT bidirectional I2C data (serial data interface for an I2C EEPROM when SMBUSz = 1) or SMBus data (serial data interface for an SMBus host when SMBUSz = 0); can be left unconnected if the external interface is not implemented.
38 SCL/SMBCLK bidirectional I2C clock (serial clock interface for an I2C EEPROM when SMBUSz = 1) or SMBus clock (serial clock interface for an SMBus host when SMBUSz = 0); can be left unconnected if the external interface is not implemented.
39 SMBUSz/SS_SUSPEND bidirectional Sampled at reset to select I2C mode (1) or SMBus mode (0); after reset it indicates the SuperSpeed USB suspend status of the upstream port (1 = suspended) when enabled through the Additional Feature Configuration register.
40 FULLPWRMGMTz/SMBA1/SS_UP bidirectional Sampled at reset to enable full power management (0 = power switching and over-current inputs supported, 1 = not supported), sets SMBus address bit 1 when SMBus is enabled, and after reset indicates SuperSpeed upstream connection status (1 = connected); power switching must be supported for battery charging applications.
41 PWRCTL_POL bidirectional Sampled at reset to set the polarity of PWRCTL[4:1] (0 = active low, 1 = active high).
42 GANGED/SMBA2/HS_UP bidirectional Sampled at reset to select individual (0) or ganged (1) power control when power switching is enabled, sets SMBus address bit 2 when SMBus is enabled, and after reset indicates High-speed upstream connection status (1 = connected); individual power control must be enabled for battery charging applications.
43 OVERCUR4z input Port 4 over-current detection input from the downstream power switch (0 = over-current event has occurred, 1 = not occurred); may be left unconnected if power management is not implemented.
44 OVERCUR3z input Port 3 over-current detection input from the downstream power switch (0 = over-current event has occurred, 1 = not occurred); may be left unconnected if power management is not implemented.
45 AUTOENz/HS_SUSPEND bidirectional Sampled at reset to enable automatic charge mode (0 = enabled on battery-charging ports when the hub is unconnected, 1 = disabled); after reset it indicates High-speed upstream suspend status (1 = suspended) when enabled through the Additional Feature Configuration register.
46 OVERCUR1z input Port 1 over-current detection input from the downstream power switch (0 = over-current event has occurred, 1 = not occurred); may be left unconnected if power management is not implemented.
47 OVERCUR2z input Port 2 over-current detection input from the downstream power switch (0 = over-current event has occurred, 1 = not occurred); may be left unconnected if power management is not implemented.
48 USB_VBUS input Upstream port VBUS detection input that must be connected to VBUS through a 90.9-kΩ ±1% resistor and to ground through a 10-kΩ ±1% resistor.
49 TEST input Pin reserved for factory test (internal pull-down).
50 GRSTz input Global power reset (active low, internal pull-up); asserting it returns all internal registers to default states and the device is completely nonfunctional while asserted.
51 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
52 VDD33 power_in 3.3-V power rail; recommended supply range is 3.0 V to 3.6 V (3.3 V nominal).
53 USB_DP_UP bidirectional USB High-speed differential transceiver (positive) for the upstream port.
54 USB_DM_UP bidirectional USB High-speed differential transceiver (negative) for the upstream port.
55 USB_SSTXP_UP output USB SuperSpeed transmitter differential pair (positive) for the upstream port.
56 USB_SSTXM_UP output USB SuperSpeed transmitter differential pair (negative) for the upstream port.
57 VDD power_in 1.1-V power rail; recommended supply range is 0.99 V to 1.26 V (1.1 V nominal).
58 USB_SSRXP_UP input USB SuperSpeed receiver differential pair (positive) for the upstream port.
59 USB_SSRXM_UP input USB SuperSpeed receiver differential pair (negative) for the upstream port.
60 NC unconnected No connect; leave floating.
61 XO output Crystal output for the internal oscillator; may be left unconnected if XI is driven by an external oscillator, and with a crystal a 1-MΩ feedback resistor is required between XI and XO.
62 XI input Crystal input for the internal oscillator, which may alternately be driven by an external oscillator output; with a crystal, a 1-MΩ feedback resistor is required between XI and XO.
63 VDD33 power_in 3.3-V power rail; recommended supply range is 3.0 V to 3.6 V (3.3 V nominal).
64 USB_R1 input Precision resistor reference; a 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH 2 V VDD33 10
Low-level input voltage VIL 0 0.8 V VDD33 10
Low-level input voltage (JTAG pins) VIL 0 0.55 V JTAG pins only 10
Input voltage VI 0 V Maximum printed as VDD33 (not numeric) 10
Output voltage VO 0 V Maximum printed as VDD33 (not numeric) 10
Input transition time (trise and tfall) tt 0 25 ns 10
High-level output voltage VOH 2.4 V VDD33, IOH = -4 mA 10
Low-level output voltage VOL 0.4 V VDD33, IOL = 4 mA 10
High-impedance output current IOZ -20 20 µA VDD33, VI = 0 to VDD33 10
High-impedance output current with internal pullup or pulldown resistor IOZP -250 250 µA VDD33, VI = 0 to VDD33 10
Input current II -15 15 µA VDD33, VI = 0 to VDD33 10
1.1V supply voltage VDD 0.99 1.1 1.26 V 9
3.3V supply voltage VDD33 3 3.3 3.6 V 9
Voltage at USB_VBUS pad USB_VBUS 0 1.155 V 9
Operating free-air temperature (TUSB8041, commercial) TA 0 70 °C TUSB8041 9
Operating junction temperature TJ -40 105 °C 9
Steady-state supply voltage (core) VDD -0.3 1.4 V Steady-state 9
Steady-state supply voltage (I/O) VDD33 -0.3 3.8 V Steady-state 9
Voltage range, USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals -0.3 1.4 V 9
Voltage range, XI terminals -0.3 2.45 V 9
Voltage range, all other terminals -0.3 3.8 V 9
Storage temperature Tstg -65 150 °C 9
VDD and VDD33 stable before de-assertion of GRSTz td2 3 ms Printed as minimum reset duration; single value placed in MIN column by assumption 11
Setup for MISC inputs sampled at de-assertion of GRSTz tsu_io 0.1 µs Sampled at de-assertion of GRSTz 11
Hold for MISC inputs sampled at de-assertion of GRSTz thd_io 0.1 µs Sampled at de-assertion of GRSTz 11
VDD33 supply ramp requirements tVDD33_RAMP 0.2 100 ms 11
VDD supply ramp requirements tVDD_RAMP 0.2 100 ms 11
Junction-to-ambient thermal resistance (RGC, 64 pins) RθJA 26 °C/W JESD51-2a natural convection, JEDEC high-K board 10
Junction-to-case (top) thermal resistance (RGC, 64 pins) RθJCtop 11.5 °C/W Cold-plate simulation on package top (applies to GRSTz) 10
Junction-to-board thermal resistance (RGC, 64 pins) RθJB 5.3 °C/W Ring cold-plate, PCB temperature controlled (JESD51-8); applies to pins with internal pullups/pulldowns 10
Junction-to-top characterization parameter (RGC, 64 pins) ψJT 0.2 °C/W JESD51-2a; applies to external input buffers 10
Junction-to-board characterization parameter (RGC, 64 pins) ψJB 5.2 °C/W JESD51-2a 10
Junction-to-case (bottom) thermal resistance (RGC, 64 pins) RθJCbot 1 °C/W Cold-plate simulation on exposed power pad 10

CAD (KiCad official)

  • Symbol: TUSB8041RGCT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: tusb8041rgct-etched.step / tusb8041rgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb8041rgct.step / tusb8041rgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 fbab35d6db2e54aa, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF