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Contents

README

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CA-IS3740LN

Chipanalog · Digital Isolators · SOIC-16

CA-IS3740LN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in A-side supply voltage, recommended range 2.375 V to 5.5 V (3.3 V or 5.0 V typical) with absolute maximum 7.0 V.
2 GNDA power_in A-side ground reference point for the A-side logic inputs and supply.
3 VI1 input A-side logic input for channel 1, TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V, Schmitt-trigger input.
4 VI2 input A-side logic input for channel 2, TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V, Schmitt-trigger input.
5 VI3/VO3 input On CA-IS3740 this pin is the A-side logic input for channel 3, TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V.
6 VI4/VO4 input On CA-IS3740 this pin is the A-side logic input for channel 4, TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V.
7 NC unconnected No internal connection on CA-IS3740; the pin may be left floating or connected to VDD or GND.
8 GNDA power_in A-side ground reference point, second A-side ground pin.
9 GNDB power_in B-side ground reference point for the B-side outputs and supply.
10 ENB input B-side output enable, active high; internally pulled up to local VDD so it may be left floating, but a defined logic level is recommended in noisy environments, and a low level puts the B-side outputs in high impedance.
11 VI4/VO4 output On CA-IS3740 this pin is the B-side logic output for channel 4, with typical output impedance of 50 Ω.
12 VI3/VO3 output On CA-IS3740 this pin is the B-side logic output for channel 3, with typical output impedance of 50 Ω.
13 VO2 output B-side logic output for channel 2, with typical output impedance of 50 Ω.
14 VO1 output B-side logic output for channel 1, with typical output impedance of 50 Ω.
15 GNDB power_in B-side ground reference point, second B-side ground pin.
16 VDDB power_in B-side supply voltage, recommended range 2.375 V to 5.5 V (3.3 V or 5.0 V typical) with absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB (absolute maximum) VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx, ENx (absolute maximum) Vin -0.5 V Printed max is VDD+0.5 (footnote 3: not to exceed 7 V) 5
Output current (absolute maximum) IO -20 20 mA 5
Junction temperature (absolute maximum) TJ 150 °C 5
Storage temperature range (absolute maximum) TSTG -65 150 °C 5
Supply voltage VDDA, VDDB (recommended) VDDA, VDDB 2.375 5.5 V Printed typ is 3.3/5.0 5
VDD undervoltage threshold, rising VDD(UVLO+) 1.95 2.24 2.37 V 5
VDD undervoltage threshold, falling VDD(UVLO-) 1.88 2.1 2.325 V 5
VDD undervoltage hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO = 5 V 5
High-level output current IOH -2 mA VDDO = 3.3 V 5
High-level output current IOH -1 mA VDDO = 2.5 V 5
Low-level output current IOL 4 mA VDDO = 5 V 5
Low-level output current IOL 2 mA VDDO = 3.3 V 5
Low-level output current IOL 1 mA VDDO = 2.5 V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signaling data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Output voltage logic low VOL 0.2 0.4 V 5 V ±10%; IOL = 4mA 9
Input threshold logic high VIT+(IN) 2 V 5 V ±10% 9
Input threshold logic low VIT-(IN) 0.8 V 5 V ±10% 9
Input high-level leakage current IIH 20 µA 5 V ±10%; VIH = VDDA at Ax, Bx or ENx 9
Input low-level leakage current IIL -20 µA 5 V ±10%; VIL = 0 V at Ax, Bx or ENx 9
Common-mode transient immunity CMTI 100 150 kV/µs 5 V ±10%; VI = VDDI1 or 0 V, VCM = 1200 V 9
Quiescent supply current IDDA, enable off, CA-IS3740L IDDA 1.3 2.1 mA 5 V ±10%; ENB = 0 V; VIN = 0 V (CA-IS3740L) 10
Quiescent supply current IDDB, enable off, CA-IS3740L IDDB 2.5 3.5 mA 5 V ±10%; ENB = 0 V; VIN = 0 V (CA-IS3740L) 10
Supply current IDDA, enable off, CA-IS3740L IDDA 6.4 9.5 mA 5 V ±10%; ENB = 0 V; VIN = VDDA (CA-IS3740L) 10
Supply current IDDB, enable off, CA-IS3740L IDDB 2.7 3.6 mA 5 V ±10%; ENB = 0 V; VIN = VDDA (CA-IS3740L) 10
Supply current IDDA, DC signal, CA-IS3740L IDDA 1.3 2.1 mA 5 V ±10%; ENB = VDDB; VIN = 0 V (CA-IS3740L) 10
Supply current IDDB, DC signal, CA-IS3740L IDDB 2.7 3.9 mA 5 V ±10%; ENB = VDDB; VIN = 0 V (CA-IS3740L) 10
Supply current IDDA, DC signal, CA-IS3740L IDDA 6.4 9.5 mA 5 V ±10%; ENB = VDDB; VIN = VDDA (CA-IS3740L) 10
Supply current IDDB, DC signal, CA-IS3740L IDDB 2.7 4 mA 5 V ±10%; ENB = VDDB; VIN = VDDA (CA-IS3740L) 10
Supply current IDDA, AC signal 1 Mbps IDDA 3.9 5.8 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 1 Mbps; CL = 15 pF 10
Supply current IDDB, AC signal 1 Mbps IDDB 4.4 6.1 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 1 Mbps; CL = 15 pF 10
Supply current IDDA, AC signal 10 Mbps IDDA 3.9 5.8 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 10 Mbps; CL = 15 pF 10
Supply current IDDB, AC signal 10 Mbps IDDB 18.7 24.8 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 10 Mbps; CL = 15 pF 10
Supply current IDDA, AC signal 100 Mbps IDDA 4.7 6.8 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 100 Mbps; CL = 15 pF 10
Supply current IDDB, AC signal 100 Mbps IDDB 41 54.7 mA 5 V ±10%; ENB = VDDB; 50% duty 5 V square wave; 100 Mbps; CL = 15 pF 10
Output voltage logic high VOH 4.8 V 5 V ±10%; IOH = -4mA; min printed as VDDO-0.4 9
Output voltage logic high VOH 3.1 V 3.3 V ±10%; IOH = -2mA; min printed as VDDO-0.4 9
Output voltage logic high VOH 2.3 V 2.5 V ±5%; IOH = -1mA; min printed as VDDO-0.4 9
Junction-to-ambient thermal resistance, SOIC16-NB RθJA 96.2 °C/W SOIC16-NB (N) package 6

CAD (KiCad official)

  • Symbol: CA-IS3740LN
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3740ln-etched.step / ca-is3740ln-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3740ln.step / ca-is3740ln.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 fd7bb5373a55db4c, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF