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CH546L

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WCH(Jiangsu Qin Heng) Pre-ordered Products, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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CH546L

WCH(Jiangsu Qin Heng) · Pre-ordered Products · LQFP-48(7x7)

CH546L from WCH(Jiangsu Qin Heng), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.6 bidirectional GPIO P1.6 with SPI0 MISO and ADC/touch-key input AIN6 on the CH546L.
2 P1.7 bidirectional GPIO P1.7 with SPI0 SCK and ADC/touch-key input AIN7.
3 P5.7/RST input External reset input with built-in pull-down resistor; also GPIO input P5.7 (RST enabled by En_P5.7_RESET configuration bit).
4 P3.0/RXD bidirectional GPIO P3.0 with UART0 serial data input RXD.
5 P4.5 bidirectional General-purpose I/O P4.5.
6 P4.4 bidirectional General-purpose I/O P4.4.
7 P3.1/TXD bidirectional GPIO P3.1 with UART0 serial data output TXD.
8 P3.2/INT0 bidirectional GPIO P3.2 with external interrupt 0 input INT0.
9 P3.3/INT1 bidirectional GPIO P3.3 with external interrupt 1 input INT1.
10 P3.4/T0 bidirectional GPIO P3.4 with Timer0 external input T0.
11 P3.5/T1 bidirectional GPIO P3.5 with Timer1 external input T1.
12 P3.6 bidirectional General-purpose I/O P3.6.
13 P3.7/INT3 bidirectional GPIO P3.7 with external interrupt 3 input INT3.
14 P4.3 bidirectional General-purpose I/O P4.3.
15 P4.2 bidirectional General-purpose I/O P4.2.
16 P4.6/XI bidirectional GPIO P4.6 or external crystal oscillator input XI (also external clock input, with XO left floating).
17 XO output External crystal oscillator inverting output; leave floating when an external clock is fed into XI.
18 GND power_in Common ground (VSS).
19 P4.1 bidirectional General-purpose I/O P4.1.
20 P4.0 bidirectional General-purpose I/O P4.0.
21 P2.0 bidirectional General-purpose I/O P2.0.
22 P2.1 bidirectional General-purpose I/O P2.1.
23 P2.2/INT0_ bidirectional GPIO P2.2 with INT0 pin-mapping alternate (INT0_); PWM3 is not available on CH546L.
24 P2.3 bidirectional General-purpose I/O P2.3.
25 P2.4/PWM1/T2_ bidirectional GPIO P2.4 with PWM1 output and T2 pin-mapping alternate (T2_).
26 P2.5/PWM0/T2EX_/CAP2_ bidirectional GPIO P2.5 with PWM0 output and T2EX/CAP2 pin-mapping alternates (T2EX_/CAP2_).
27 P2.6 bidirectional General-purpose I/O P2.6 (UART1 not available on CH546L).
28 P2.7 bidirectional General-purpose I/O P2.7 (UART1 not available on CH546L).
29 P5.5/HVOD output Open-drain output P5.5 supporting up to 12V high-voltage pull-up (HVOD).
30 P5.4/ALE/CKO output Output P5.4 providing pseudo address latch ALE or divided system clock output CKO.
31 P5.1/DP bidirectional USB device D+ signal (UDP) with built-in resistor, no external series resistor recommended; also P5.1 with controllable pull-down.
32 P5.0/DM bidirectional USB device D- signal (UDM) with built-in resistor, no external series resistor recommended; also P5.0 with controllable pull-down.
33 P0.7 bidirectional General-purpose I/O P0.7.
34 P0.6 bidirectional General-purpose I/O P0.6.
35 P0.5 bidirectional General-purpose I/O P0.5.
36 P0.4 bidirectional General-purpose I/O P0.4.
37 P0.3/TXD_ bidirectional GPIO P0.3 with UART0 TXD pin-mapping alternate (TXD_).
38 P0.2/RXD_ bidirectional GPIO P0.2 with UART0 RXD pin-mapping alternate (RXD_).
39 P0.1 bidirectional General-purpose I/O P0.1.
40 P0.0 bidirectional General-purpose I/O P0.0.
41 VDD power_in I/O supply input and external supply input of the internal USB regulator (2.8V to 5V range per datasheet); requires a 0.1uF decoupling capacitor.
42 V33 passive Internal USB regulator output and USB supply input; connect to VDD when supply is below 3.6V, otherwise connect a 0.1uF decoupling capacitor.
43 P1.0/T2/AIN0 bidirectional GPIO P1.0 with Timer2 external input/clock output T2 and ADC/touch-key input AIN0.
44 P1.1/T2EX/CAP2/AIN1 bidirectional GPIO P1.1 with Timer2 reload/capture input T2EX/CAP2 and ADC/touch-key input AIN1.
45 P1.2/AIN2 bidirectional GPIO P1.2 with ADC/touch-key input AIN2.
46 P1.3/AIN3 bidirectional GPIO P1.3 with ADC/touch-key input AIN3.
47 P1.4/SCS/AIN4 bidirectional GPIO P1.4 with SPI0 chip-select input SCS and ADC/touch-key input AIN4.
48 P1.5/MOSI/PWM0_/AIN5 bidirectional GPIO P1.5 with SPI0 MOSI, PWM0 pin-mapping alternate (PWM0_) and ADC/touch-key input AIN5.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-48(7x7)
Category Solders / Accessories / Batteries
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature TA -40 85 ℃ Fsys<40MHz 58
Ambient temperature for Flash-ROM/EEPROM erase/program (recommended) TAROM -20 85 ℃ 58
Storage temperature TS -55 125 ℃ 58
Supply voltage VDD -0.4 7 V VDD to supply, GND to ground 58
Internal USB supply voltage V33 -0.4 V max printed as VDD+0.4 58
Voltage on input or output pin VIO -0.4 V max printed as VDD+0.4 58
Voltage on UDP/UDM pins VIOU -0.4 V max printed as V33+0.4 58
Voltage on P5.5/HVOD pin VIOHV -0.4 13 V 58
VDD supply voltage (5V mode) VDD5 3.7 5 6.5 V V33 external capacitor only; TA=25℃, VDD=5V, Fsys=12MHz 58
Internal regulator output voltage V33 3.23 3.3 3.38 V TA=-15～65℃ 58
Internal regulator output voltage V33 3.2 3.3 3.4 V TA=-40～85℃ 58
Standby/normal sleep supply current 5V ISLP5 1.1 1.5 mA 58
Power-down/deep sleep supply current 5V ISLP5L 4 40 uA bLDO_3V3_OFF=1 58
ADC operating current 5V IADC5 200 800 uA 58
Comparator operating current 5V ICMP5 100 500 uA 58
Touch-key charge current 5V ITKEY5 35 50 70 uA 58
Low-level input voltage 5V VIL5 0 1.2 V 58
High-level input voltage 5V VIH5 2.4 V max printed as VDD 58
Low-level output voltage 5V VOL5 0.4 V 15mA sink current 58
P5.5/HVOD pin voltage (no output/high-Z) VHVOD 0 12 12.6 V VDD=5V 58
Input current, no pull-up input IIN -5 0 5 uA 58
Input current with pull-down 5V IDN5 -35 -70 -140 uA 58
Input current with pull-up 5V IUP5 35 70 140 uA 58
Input current with pull-up, low-to-high transition 5V IUP5X 250 400 600 uA 58
Analog switch on-resistance 5V Rsw5 500 700 1350 Ω 58
Power-on reset threshold 5V Vpot 2.3 4 4.6 V VDD=5V 59
VDD supply voltage (3.3V mode, USB on) VDD3 3 3.3 3.6 V V33 shorted to VDD, USB enabled 59
VDD supply voltage (3.3V mode, USB off) VDD3 2.7 3.3 3.6 V V33 shorted to VDD, USB disabled 59
Standby/normal sleep supply current 3.3V ISLP3 1.1 1.5 mA 59
Power-down/deep sleep supply current 3.3V ISLP3L 3 25 uA bLDO_3V3_OFF=1 59
ADC operating current 3.3V IADC3 180 700 uA 59
Comparator operating current 3.3V ICMP3 70 300 uA 59
Touch-key charge current 3.3V ITKEY3 35 50 70 uA 59
Low-level input voltage 3.3V VIL3 0 0.8 V 59
High-level input voltage 3.3V VIH3 1.9 V max printed as VDD 59
Low-level output voltage 3.3V VOL3 0.4 V 10mA sink current 59
P5.5/HVOD pin voltage (no output/high-Z) VHVOD 0 12 12.6 V VDD=V33=3.3V 59
Input current with pull-down 3.3V IDN3 -15 -30 -60 uA 59
Input current with pull-up 3.3V IUP3 15 30 60 uA 59
Input current with pull-up, low-to-high transition 3.3V IUP3X 100 170 250 uA 59
Analog switch on-resistance 3.3V Rsw3 600 1000 2500 Ω 59
Power-on reset threshold 3.3V Vpot 2.3 2.7 3 V VDD=V33=3.3V 59
External crystal / XI input clock frequency Fxt 6 24 24 MHz 59
Calibrated internal clock frequency Fosc 23.52 24 24.48 MHz VDD>=3V, TA=-15～65℃ 59
Calibrated internal clock frequency Fosc 23.38 24 24.72 MHz VDD>=3V, TA=-40～85℃ 59
Calibrated internal clock frequency, VDD<3V Fosc3 23.1 24 24.9 MHz VDD<3V 59
USB sampling clock frequency Fusb4x 47.04 48 48.96 MHz USB function used 59
System clock frequency Fsys 0.1 12 40 MHz VDD>=3V 59
System clock frequency Fsys 0.1 12 24 MHz VDD<3V 59
Power-on reset delay Tpor 8 11 15 mS 59
Hot reset delay Trdl 20 30 50 uS 59

CAD (KiCad official)

  • Symbol: CH546L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch546l-etched.step / ch546l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch546l.step / ch546l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (61 pp, sha256 da4affda6c33d6a6, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF