component
CA3140MZ96
Public Made by Adomby adom
RENESAS Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA3140MZ96
RENESAS · Operational Amplifier · SOIC-8
CA3140MZ96 from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OFFSET NULL | passive | Provided for input offset voltage nulling in applications that require it. |
| 2 | INV. INPUT | input | Inverting input of the PMOS input stage, which gives very high input impedance (1.5T typ) and very low input current (10pA typ at 15V). |
| 3 | NON-INV. INPUT | input | Non-inverting input of the PMOS input stage; common mode input can be swung 0.5V below the negative supply rail. |
| 4 | V- | power_in | Negative supply terminal; the part operates from 4V to 36V total supply, single or dual. |
| 5 | OFFSET NULL | passive | Second input offset voltage nulling terminal, used together with pin 1. |
| 6 | OUTPUT | output | Bipolar output stage with built-in protection against load short circuits to either supply rail or to ground. |
| 7 | V+ | power_in | Positive supply terminal; the part operates from 4V to 36V total supply, single or dual. |
| 8 | STROBE | passive | Listed on the pinout, but the function of this terminal is not described in the provided pages. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | /VIO/ | 5 | 15 | mV | VSUPPLY = 15V, TA = 25oC | 3 | |
| Input Offset Current | /IIO/ | 0.5 | 30 | pA | VSUPPLY = 15V, TA = 25oC | 3 | |
| Input Current | II | 10 | 50 | pA | VSUPPLY = 15V, TA = 25oC | 3 | |
| Large Signal Voltage Gain | AOL | 20 | 100 | kV/V | VSUPPLY = 15V, TA = 25oC; VO = 26VP-P, +12V, -14V, RL = 2k (Note 3) | 4 | |
| Large Signal Voltage Gain | AOL | 86 | 100 | dB | VSUPPLY = 15V, TA = 25oC; VO = 26VP-P, +12V, -14V, RL = 2k (Note 3) | 4 | |
| Common Mode Rejection Ratio | CMRR | 32 | 320 | V/V | VSUPPLY = 15V, TA = 25oC; See Figure 34 | 4 | |
| Common Mode Rejection Ratio | CMRR | 70 | 90 | dB | VSUPPLY = 15V, TA = 25oC; See Figure 34 | 4 | |
| Common Mode Input Voltage Range (lower limit as printed in MIN column) | VICR | -15 | V | VSUPPLY = 15V, TA = 25oC; See Figure 8 | 4 | ||
| Power-Supply Rejection Ratio | PSRR | 100 | 150 | V/V | VSUPPLY = 15V, TA = 25oC; VIO/VS (See Figure 36) | 4 | |
| Power-Supply Rejection Ratio | PSRR | 76 | 80 | dB | VSUPPLY = 15V, TA = 25oC; VIO/VS (See Figure 36) | 4 | |
| Max Output Voltage (positive) | VOM+ | 12 | 13 | V | VSUPPLY = 15V, TA = 25oC; RL = 2k (Note 4) | 4 | |
| Max Output Voltage (negative) | VOM- | -14 | -14.4 | V | VSUPPLY = 15V, TA = 25oC; RL = 2k (Note 4) | 4 | |
| Supply Current | I+ | 4 | 6 | mA | VSUPPLY = 15V, TA = 25oC; See Figure 32 | 4 | |
| Device Dissipation | PD | 120 | 180 | mW | VSUPPLY = 15V, TA = 25oC | 4 | |
| DC Supply Voltage (between V+ and V- terminals) | 36 | V | 3 | ||||
| Differential Mode Input Voltage | 8 | V | 3 | ||||
| Input Terminal Current | 1 | mA | 3 | ||||
| Maximum Junction Temperature (Plastic Package) | 150 | oC | 3 | ||||
| Maximum Storage Temperature Range | -65 | 150 | oC | 3 | |||
| Maximum Lead Temperature (Soldering) | 300 | oC | Soldering 10s, SOIC - Lead Tips Only | 3 | |||
| Supply Voltage Range (single or dual supply) | 4 | 36 | V | Stated in Description text | 1 | ||
| Operating Temperature Range | TA | -55 | 125 | oC | 3 | ||
| Thermal Resistance, Junction-to-Ambient (SOIC package) | JA | 165 | oC/W | Typical, Note 1: measured on low effective thermal conductivity test board in free air | 3 |
CAD (KiCad official)
- Symbol:
CA3140MZ96 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ca3140mz96-etched.step/ca3140mz96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca3140mz96.step/ca3140mz96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (24 pp, sha256
e848f94eb236d01b, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).