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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32G0B1RCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32G0B1RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC11	bidirectional	5 V tolerant (FT) I/O with alternate functions USART3_RX, USART4_RX, TIM1_CH4, SPI3_MISO.
2	PC12	bidirectional	5 V tolerant (FT) I/O with alternate functions LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1, USART5_TX, SPI3_MOSI.
3	PC13	bidirectional	FT I/O supplied via the power switch (3 mA sink limit, output speed max 2 MHz with 30 pF load, not for driving LEDs); TIM1_BKIN, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
4	PC14-OSC32_IN	bidirectional	FT I/O supplied via the power switch (3 mA sink limit, max 2 MHz with 30 pF load) that serves as the LSE 32.768 kHz oscillator input OSC32_IN; alternate TIM1_BKIN2.
5	PC15-OSC32_OUT	bidirectional	FT I/O supplied via the power switch (3 mA sink limit, max 2 MHz with 30 pF load) that serves as the LSE oscillator output OSC32_OUT; alternates OSC32_EN, OSC_EN, TIM15_BKIN.
6	VBAT	power_in	Backup supply (1.55 V to 3.6 V) for RTC, TAMP, LSE oscillator and backup registers when VDD is not present.
7	VREF+	power_in	Analog reference voltage input, or the output of the internal voltage reference buffer (VREFBUF_OUT); VREF+ must equal VDDA when VDDA < 2 V and be between 2 V and VDDA otherwise.
8	VDD/VDDA	power_in	Main digital and analog supply (1.7 V to 3.6 V) for the regulator, I/Os, ADC, DAC, comparators and VREFBUF; decouple with 100 nF + 4.7 uF to VSS.
9	VSS/VSSA	power_in	Ground for the digital and analog supplies.
10	PF0-OSC_IN	bidirectional	FT I/O that serves as the 4-48 MHz HSE oscillator input OSC_IN; alternates CRS1_SYNC, EVENTOUT, TIM14_CH1.
11	PF1-OSC_OUT	bidirectional	FT I/O that serves as the HSE oscillator output OSC_OUT; alternates OSC_EN, EVENTOUT, TIM15_CH1N.
12	PF2-NRST	bidirectional	Bidirectional active-low reset pin with embedded weak pull-up; also GPIO PF2 with MCO, LPUART2_TX, LPUART2_RTS_DE.
13	PC0	bidirectional	FT_a I/O with analog switch; LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1, LPUART2_TX, USART6_TX, I2C3_SCL, COMP3_OUT.
14	PC1	bidirectional	FT_a I/O with analog switch; LPTIM1_OUT, LPUART1_TX, TIM15_CH1, LPUART2_RX, USART6_RX, I2C3_SDA; additional function COMP3_INP1.
15	PC2	bidirectional	FT I/O with LPTIM1_IN2, SPI2_MISO/I2S2_MCK, TIM15_CH2, FDCAN2_RX, COMP3_OUT.
16	PC3	bidirectional	FT I/O with LPTIM1_ETR, SPI2_MOSI/I2S2_SD, LPTIM2_ETR, FDCAN2_TX.
17	PA0	bidirectional	FT_a I/O with SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX; analog COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1.
18	PA1	bidirectional	FT_ea I/O (switchable diode to VDD) with SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, I2C1_SMBA; analog COMP1_INP2, ADC_IN1.
19	PA2	bidirectional	FT_a I/O with SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, LPUART1_TX, COMP2_OUT; analog COMP2_INM8, ADC_IN2, WKUP4, LSCO.
20	PA3	bidirectional	FT_ea I/O with SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, LPUART1_RX; analog COMP2_INP2, ADC_IN3.
21	PA4	bidirectional	3.6 V tolerant (TT_a) I/O with SPI1_NSS/I2S1_WS, USB_NOE, USART6_TX, TIM14_CH1, SPI3_NSS; analog ADC_IN4, DAC1_OUT1, RTC_OUT2.
22	PA5	bidirectional	TT_ea I/O with SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX; analog ADC_IN5, DAC1_OUT2.
23	PA6	bidirectional	FT_ea I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, I2C2_SDA, I2C3_SDA; analog ADC_IN6.
24	PA7	bidirectional	FT_a I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, I2C2_SCL, I2C3_SCL; analog ADC_IN7.
25	PC4	bidirectional	FT_a I/O with USART3_TX, USART1_TX, TIM2_CH1_ETR, FDCAN1_RX; analog COMP1_INM7, ADC_IN17.
26	PC5	bidirectional	FT_a I/O with USART3_RX, USART1_RX, TIM2_CH2, FDCAN1_TX; analog COMP1_INP0, ADC_IN18, WKUP5.
27	PB0	bidirectional	FT_ea I/O with SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, USART5_TX; analog COMP3_INP0, ADC_IN8.
28	PB1	bidirectional	FT_ea I/O with TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, USART5_RX; analog COMP1_INM6, ADC_IN9.
29	PB2	bidirectional	FT_ea I/O with SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT; analog COMP1_INP1, COMP3_INM6, ADC_IN10.
30	PB10	bidirectional	FT_fa I/O (Fm+ capable) with CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL; analog ADC_IN11.
31	PB11	bidirectional	FT_fa I/O (Fm+ capable) with SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA; analog ADC_IN15.
32	PB12	bidirectional	FT_fa I/O (Fm+ capable) with SPI2_NSS/I2S2_WS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, I2C2_SMBA; analog ADC_IN16.
33	PB13	bidirectional	FT_f I/O (Fm+ capable) with SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, I2C2_SCL.
34	PB14	bidirectional	FT_f I/O (Fm+ capable) with SPI2_MISO/I2S2_MCK, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, I2C2_SDA.
35	PB15	bidirectional	FT_fc I/O (Fm+, USB Type-C PD capable) with SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2; additional UCPD1_CC2, RTC_REFIN; possible pull-down at reset.
36	PA8	bidirectional	FT_fc I/O (Fm+, USB Type-C PD capable) with MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT; additional UCPD1_CC1; possible pull-down at reset.
37	PA9	bidirectional	FT_fd I/O (Dead Battery capable) with MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, I2C1_SCL; additional UCPD1_DBCC1; can be remapped in place of PA11.
38	PC6	bidirectional	FT I/O with UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX.
39	PC7	bidirectional	FT I/O with UCPD2_FRSTX, TIM3_CH2, TIM2_CH4, LPUART2_RX.
40	PD8	bidirectional	FT I/O with USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT.
41	PD9	bidirectional	FT I/O with USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2.
42	PA10	bidirectional	FT_fd I/O (Fm+, Dead Battery capable) with SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, I2C1_SDA; additional UCPD1_DBCC2; can be remapped in place of PA12.
43	PA11 [PA9]	bidirectional	FT_f I/O with SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, I2C2_SCL; additional USB_DM; can be remapped to PA9.
44	PA12 [PA10]	bidirectional	FT_f I/O with SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2C2_SDA; additional USB_DP; can be remapped to PA10.
45	PA13	bidirectional	FT_e I/O that is SWDIO at reset with internal pull-up active; alternates IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX.
46	PA14-BOOT0	bidirectional	FT I/O that is SWCLK at reset with internal pull-down active; also BOOT0 boot selection, alternates USART2_TX, LPUART2_TX.
47	PA15	bidirectional	FT I/O with SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USB_NOE, SPI3_NSS.
48	PC8	bidirectional	FT I/O with UCPD2_FRSTX, TIM3_CH3, TIM1_CH1, LPUART2_CTS.
49	PC9	bidirectional	FT I/O with I2S_CKIN, TIM3_CH4, TIM1_CH2, LPUART2_RTS_DE, USB_NOE.
50	PD0	bidirectional	FT_c I/O (USB Type-C PD capable) with EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1, FDCAN1_RX; additional UCPD2_CC1; possible pull-down at reset.
51	PD1	bidirectional	FT_d I/O (Dead Battery capable) with EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1, FDCAN1_TX; additional UCPD2_DBCC1; possible pull-down at reset.
52	PD2	bidirectional	FT_c I/O (USB Type-C PD capable) with USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX; additional UCPD2_CC2.
53	PD3	bidirectional	FT_d I/O (Dead Battery capable) with USART2_CTS, SPI2_MISO/I2S2_MCK, TIM1_CH2N, USART5_TX; additional UCPD2_DBCC2.
54	PD4	bidirectional	FT I/O with USART2_RTS_DE_CK, SPI2_MOSI/I2S2_SD, TIM1_CH3N, USART5_RTS_DE_CK.
55	PD5	bidirectional	FT I/O with USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN, USART5_CTS.
56	PD6	bidirectional	FT I/O with USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT.
57	PB3	bidirectional	FT_a I/O with SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, I2C3_SCL, SPI3_SCK; analog COMP2_INM6.
58	PB4	bidirectional	FT_a I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, I2C3_SDA, SPI3_MISO; analog COMP2_INP0.
59	PB5	bidirectional	FT I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, SPI3_MOSI; additional WKUP6.
60	PB6	bidirectional	FT_fa I/O (Fm+ capable) with USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, I2C1_SCL, TIM4_CH1; analog COMP2_INP1.
61	PB7	bidirectional	FT_fa I/O (Fm+ capable) with USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, I2C1_SDA, TIM4_CH2; analog COMP2_INM7, PVD_IN.
62	PB8	bidirectional	FT_f I/O (Fm+ capable) with CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, I2C1_SCL, TIM4_CH3.
63	PB9	bidirectional	FT_f I/O (Fm+ capable) with IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, I2C1_SDA, TIM4_CH4.
64	PC10	bidirectional	FT I/O with USART3_TX, USART4_TX, TIM1_CH3, SPI3_SCK.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: STM32G0B1RCT6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm32g0b1rct6-etched.step / stm32g0b1rct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g0b1rct6.step / stm32g0b1rct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (159 pp, sha256 1f06714e7d03df85, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF