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SN74F377ADWR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74F377ADWR
Texas Instruments · Flip Flops · SOIC-20-300mil
SN74F377ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE | input | Latched clock enable; when CE is low, D data is transferred to Q on the positive-going CLK edge, and when CE is high, Q holds its state. |
| 2 | 1Q | output | Single-rail output of flip-flop 1, updated from 1D on the positive-going CLK edge when CE is low. |
| 3 | 1D | input | Data input of flip-flop 1; must meet the setup and hold times around the CLK rising edge (setup 2.5 ns with CE high, 4 ns with CE low at 4.5 V to 5.5 V). |
| 4 | 2D | input | Data input of flip-flop 2; must meet the setup and hold times around the CLK rising edge. |
| 5 | 2Q | output | Single-rail output of flip-flop 2, updated from 2D on the positive-going CLK edge when CE is low. |
| 6 | 3Q | output | Single-rail output of flip-flop 3, updated from 3D on the positive-going CLK edge when CE is low. |
| 7 | 3D | input | Data input of flip-flop 3; must meet the setup and hold times around the CLK rising edge. |
| 8 | 4D | input | Data input of flip-flop 4; must meet the setup and hold times around the CLK rising edge. |
| 9 | 4Q | output | Single-rail output of flip-flop 4, updated from 4D on the positive-going CLK edge when CE is low. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | CLK | input | Common clock input; data is transferred on the positive-going edge, with a maximum clock frequency of 110 MHz over 4.5 V to 5.5 V. |
| 12 | 5Q | output | Single-rail output of flip-flop 5, updated from 5D on the positive-going CLK edge when CE is low. |
| 13 | 5D | input | Data input of flip-flop 5; must meet the setup and hold times around the CLK rising edge. |
| 14 | 6D | input | Data input of flip-flop 6; must meet the setup and hold times around the CLK rising edge. |
| 15 | 6Q | output | Single-rail output of flip-flop 6, updated from 6D on the positive-going CLK edge when CE is low. |
| 16 | 7Q | output | Single-rail output of flip-flop 7, updated from 7D on the positive-going CLK edge when CE is low. |
| 17 | 7D | input | Data input of flip-flop 7; must meet the setup and hold times around the CLK rising edge. |
| 18 | 8D | input | Data input of flip-flop 8; must meet the setup and hold times around the CLK rising edge. |
| 19 | 8Q | output | Single-rail output of flip-flop 8, updated from 8D on the positive-going CLK edge when CE is low. |
| 20 | VCC | power_in | Supply pin; recommended supply voltage is 4.5 V to 5.5 V (absolute maximum 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74F377ADWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
sn74f377adwr-etched.step/sn74f377adwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74f377adwr.step/sn74f377adwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
27c64b5732e40611, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).