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SN74HC374NSR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC374NSR
Texas Instruments · Flip Flops · SOIC-20-208mil
SN74HC374NSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low three-state output enable; when HIGH all Q outputs enter high-impedance state; does not affect internal flip-flop operation; VIH min 3.15 V at VCC = 4.5 V. |
| 2 | 1Q | tri_state | Three-state registered output of flip-flop 1; follows 1D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 3 | 1D | input | Data input for flip-flop 1; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 4 | 2D | input | Data input for flip-flop 2; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 5 | 2Q | tri_state | Three-state registered output of flip-flop 2; follows 2D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 6 | 3Q | tri_state | Three-state registered output of flip-flop 3; follows 3D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 7 | 3D | input | Data input for flip-flop 3; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 8 | 4D | input | Data input for flip-flop 4; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 9 | 4Q | tri_state | Three-state registered output of flip-flop 4; follows 4D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 10 | GND | power_in | Ground reference; continuous current through GND pin must not exceed ±70 mA. |
| 11 | CLK | input | Clock input; data at D inputs is captured on the positive (rising) edge; tsu = 20 ns min, th = 5 ns min at VCC = 4.5 V; fclock max 30 MHz at VCC = 4.5 V. |
| 12 | 5Q | tri_state | Three-state registered output of flip-flop 5; follows 5D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 13 | 5D | input | Data input for flip-flop 5; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 14 | 6D | input | Data input for flip-flop 6; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 15 | 6Q | tri_state | Three-state registered output of flip-flop 6; follows 6D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 16 | 7Q | tri_state | Three-state registered output of flip-flop 7; follows 7D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 17 | 7D | input | Data input for flip-flop 7; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 18 | 8D | input | Data input for flip-flop 8; logic level captured on positive CLK edge; VIH min 3.15 V at VCC = 4.5 V; must not be left floating. |
| 19 | 8Q | tri_state | Three-state registered output of flip-flop 8; follows 8D on positive CLK edge when OE = L; IOH = −6 mA min at VOH = 3.98 V, VCC = 4.5 V; high-impedance when OE = H. |
| 20 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; decouple with 0.1 µF capacitor as close to pin as possible; continuous current must not exceed ±70 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-208mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HC374NSR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
- 3D model files:
sn74hc374nsr-etched.step/sn74hc374nsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc374nsr.step/sn74hc374nsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
e72f5f2d1a24107d, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).