SI3402-B-GMR from SKYWORKS SILICON LABS, in a QFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EROUT	output	Error-amplifier output and PWM input; directly connected to opto-coupler in isolated application.
2	SSFT	unconnected	Legacy Si3402-A soft-start pin. The non-isolated soft-start function is internal on the Si3402-B, so this pin is not internally connected. Legacy components/connections are harmless and may be retained or deleted.
3	VDD	power_out	5 V supply rail for the switcher; provides drive for the opto-coupler.
4	ISOSSFT	unconnected	Legacy Si3402-A isolated soft-start pin. The isolated soft-start function is internal on the Si3402-B, so this pin is not internally connected. Legacy components/connections are harmless and may be retained or deleted.
5	PLOSS	output	Early power-loss indicator; open-drain output that is pulled to VPOS when VPORT is applied. Threshold is VPOS - (greater of CT1/CT2 or SP1/SP2), typ 1.5 V.
6	RDET	passive	Input pin for external precision detection resistor; also used for establishing the absolute current reference for the device.
7	HSO	power_out	Hotswap switch output; connects to VNEG through the hotswap switch. Externally tied to VSS2 (the switcher negative supply rail).
8	RCL	passive	Input pin for external precision classification resistor (RCLASS); float if optional RCLASS is unused. Sets the PoE class current (Class 0-3).
9	VNEG	power_in	Rectified high-voltage supply, negative rail. Must be connected to the thermal PAD node (VNEG) on the package bottom. The thermal pad must connect to VNEG (pin 9) as well as a >=2 in^2 heat spreader plane using a minimum of nine thermal vias.
10	SP2	power_in	High-voltage supply input from spare pair; polarity-insensitive. Paired with SP1 for the PoE spare-pair input to the internal diode bridge.
11	SP1	power_in	High-voltage supply input from spare pair; polarity-insensitive. Paired with SP2 for the PoE spare-pair input to the internal diode bridge.
12	VPOSF	power_out	Rectified high-voltage supply, positive rail (force node). Output of the internal rectification/protection block.
13	CT2	power_in	High-voltage supply input from center-tap of Ethernet transformer; polarity-insensitive. Paired with CT1 for the PoE center-tap input to the internal diode bridge.
14	CT1	power_in	High-voltage supply input from center-tap of Ethernet transformer; polarity-insensitive. Paired with CT2 for the PoE center-tap input to the internal diode bridge.
15	VSSA	power_in	Analog ground. In new designs, VSSA may be left floating for easier PCB layout, with VSS2 used as the analog ground. VSSA is internally connected to VSS2.
16	VPOSS	unconnected	Legacy Si3402-A positive-rail sense node. The positive-rail sense-node function is no longer implemented, so this pin is not internally connected.
17	VSS1	unconnected	Legacy Si3402-A negative supply rail. This former negative supply rail pin is no longer implemented, so this pin is not internally connected.
18	SWO	power_out	Switching transistor output; drain of the internal switching N-FET. Peak current 2.4 A; RDS(on) typ 0.5 ohm; switcher frequency ~350 kHz.
19	VSS2	power_in	Negative supply rail for the switcher; externally tied to HSO. Also serves as the analog-ground reference for new designs (see VSSA).
20	FB	input	Regulated feedback input for the switcher in non-isolated (buck) applications. Sets the output voltage via an external resistor divider.
PAD	VNEG	power_in	Exposed thermal pad; electrically the VNEG rectified-negative rail. Must be tied to pin 9 (VNEG) and to a >=2 in^2 heat-spreader plane through a minimum of nine thermal vias for thermal performance.

Key specifications

Parameter	Value
Manufacturer	SKYWORKS SILICON LABS
Package	QFN-20-EP(5x5)
Category	Interface
Pins	21

Ordering variants

Same part, different packaging or reel option.

SI3402-B-GMR
Si3402-B-GMR

CAD (KiCad official)

Symbol: SI3402-B-GMR
Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
3D model: QFN-20-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SKYWORKS SILICON LABS datasheet (22 pp, sha256 fd0e50110e6c9606, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF