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74hc237d

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by Ray

Nexperia Signal Switches / Encoders & Decoders / Multiplexers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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74HC237D

Nexperia · Signal Switches / Encoders & Decoders / Multiplexers · SOIC-16

74HC237D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address/data input bit 0 to the 3-bit input latch feeding the 3-to-8 decoder. CMOS-level input; VIH ≥ 3.15 V at VCC = 4.5 V, VIL ≤ 1.35 V.
2 A1 input Address/data input bit 1 to the 3-bit input latch feeding the 3-to-8 decoder. CMOS-level input; VIH ≥ 3.15 V at VCC = 4.5 V.
3 A2 input Address/data input bit 2 to the 3-bit input latch feeding the 3-to-8 decoder. CMOS-level input; VIH ≥ 3.15 V at VCC = 4.5 V.
4 LE input Latch enable input (active LOW). When LE = LOW the latches are transparent and outputs follow A0..A2; on LOW-to-HIGH transition, the address is stored and further address changes are ignored while LE is HIGH.
5 E1 input Data (output) enable input 1, active LOW. All Yn outputs are forced LOW unless E1 = LOW AND E2 = HIGH.
6 E2 input Data (output) enable input 2, active HIGH. All Yn outputs are forced LOW unless E1 = LOW AND E2 = HIGH.
7 Y7 output Decoded active-HIGH output line 7 (asserted when latched address A2:A0 = 111 and outputs are enabled). Push-pull CMOS output; IO up to ±25 mA absolute max, VOH ≥ 3.98 V at IO = -4 mA and VCC = 4.5 V.
8 GND power_in Ground reference (0 V). Return for VCC supply and all signals.
9 Y6 output Decoded active-HIGH output line 6 (asserted when latched address A2:A0 = 110 and outputs are enabled). Push-pull CMOS output.
10 Y5 output Decoded active-HIGH output line 5 (asserted when latched address A2:A0 = 101 and outputs are enabled). Push-pull CMOS output.
11 Y4 output Decoded active-HIGH output line 4 (asserted when latched address A2:A0 = 100 and outputs are enabled). Push-pull CMOS output.
12 Y3 output Decoded active-HIGH output line 3 (asserted when latched address A2:A0 = 011 and outputs are enabled). Push-pull CMOS output.
13 Y2 output Decoded active-HIGH output line 2 (asserted when latched address A2:A0 = 010 and outputs are enabled). Push-pull CMOS output.
14 Y1 output Decoded active-HIGH output line 1 (asserted when latched address A2:A0 = 001 and outputs are enabled). Push-pull CMOS output.
15 Y0 output Decoded active-HIGH output line 0 (asserted when latched address A2:A0 = 000 and outputs are enabled). Push-pull CMOS output.
16 VCC power_in Positive supply voltage. Recommended operating range 2.0 V to 6.0 V (typ 5.0 V); absolute maximum -0.5 V to +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

  • 74HC237DD
  • 74HC237DPW

CAD (KiCad official)

  • Symbol: 74HC237D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (None pp, sha256 a9d2400e7a0d9e8a, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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