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ADS4242IRGCR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersads4242irgcrfactory-2.0.0extractor-text

Verified ADS4242IRGCR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS4242IRGCR · VQFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 96-page datasheet
  • ✓distributor: lcsc C1543489, digikey ADS4242IRGCR-ND, mouser 595-ADS4242IRGCR
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rtr8ttgr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.93)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads4242irgcr.kicad_sym✓ ads4242irgcr.kicad_mod✓ ads4242irgcr.step
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Contents

README

markdown

ADS4242IRGCR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)

ADS4242IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Output buffer supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
2 DB4M output Channel B differential LVDS output data D4 and D5 multiplexed, complement.
3 DB4P output Channel B differential LVDS output data D4 and D5 multiplexed, true.
4 DB6M output Channel B differential LVDS output data D6 and D7 multiplexed, complement.
5 DB6P output Channel B differential LVDS output data D6 and D7 multiplexed, true.
6 DB8M output Channel B differential LVDS output data D8 and D9 multiplexed, complement.
7 DB8P output Channel B differential LVDS output data D8 and D9 multiplexed, true.
8 DB10M output Channel B differential LVDS output data D10 and D11 multiplexed, complement.
9 DB10P output Channel B differential LVDS output data D10 and D11 multiplexed, true.
10 DB12M output Channel B differential LVDS output data D12 and D13 multiplexed (ADS424x only), complement.
11 DB12P output Channel B differential LVDS output data D12 and D13 multiplexed (ADS424x only), true.
12 RESET input Serial interface reset input, high pulse initializes registers; must be tied high in parallel interface mode; internal 150-kΩ pulldown.
13 SCLK input Serial interface clock input when RESET is low, or low-speed mode select when RESET is high; internal 150-kΩ pulldown.
14 SDATA input Serial interface data input with internal 150-kΩ pulldown.
15 SEN input Serial interface enable input when RESET is low, or output interface and data format select when RESET is high; internal 150-kΩ pullup to AVDD.
16 AVDD power_in Analog power supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
17 AGND power_in Analog ground.
18 AGND power_in Analog ground.
19 INP_B input Differential analog positive input, channel B.
20 INM_B input Differential analog negative input, channel B.
21 AGND power_in Analog ground.
22 AVDD power_in Analog power supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
23 VCM output Outputs the 0.95 V common-mode voltage that can be used externally to bias the analog input pins.
24 AGND power_in Analog ground.
25 CLKP input Differential clock positive input.
26 CLKM input Differential clock negative input.
27 AGND power_in Analog ground.
28 AGND power_in Analog ground.
29 INP_A input Differential analog positive input, channel A.
30 INM_A input Differential analog negative input, channel A.
31 AGND power_in Analog ground.
32 AGND power_in Analog ground.
33 AVDD power_in Analog power supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
34 AVDD power_in Analog power supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
35 CTRL1 input Digital control input that together with CTRL2 and CTRL3 sets the power-down modes.
36 CTRL2 input Digital control input that together with CTRL1 and CTRL3 sets the power-down modes.
37 CTRL3 input Digital control input that together with CTRL1 and CTRL2 sets the power-down modes.
38 NC unconnected Do not connect, must be floated.
39 NC unconnected Do not connect, must be floated.
40 DA0M output Channel A differential LVDS output data D0 and D1 multiplexed, complement.
41 DA0P output Channel A differential LVDS output data D0 and D1 multiplexed, true.
42 DA2M output Channel A differential LVDS output data D2 and D3 multiplexed, complement.
43 DA2P output Channel A differential LVDS output data D2 and D3 multiplexed, true.
44 DA4M output Channel A differential LVDS output data D4 and D5 multiplexed, complement.
45 DA4P output Channel A differential LVDS output data D4 and D5 multiplexed, true.
46 DA6M output Channel A differential LVDS output data D6 and D7 multiplexed, complement.
47 DA6P output Channel A differential LVDS output data D6 and D7 multiplexed, true.
48 DRVDD power_in Output buffer supply, recommended 1.7 V to 1.9 V (1.8 V nominal).
49 DRGND power_in Output buffer ground.
50 DA8M output Channel A differential LVDS output data D8 and D9 multiplexed, complement.
51 DA8P output Channel A differential LVDS output data D8 and D9 multiplexed, true.
52 DA10M output Channel A differential LVDS output data D10 and D11 multiplexed, complement.
53 DA10P output Channel A differential LVDS output data D10 and D11 multiplexed, true.
54 DA12M output Channel A differential LVDS output data D12 and D13 multiplexed (ADS424x only), complement.
55 DA12P output Channel A differential LVDS output data D12 and D13 multiplexed (ADS424x only), true.
56 CLKOUTM output Differential output clock, complement.
57 CLKOUTP output Differential output clock, true.
58 NC unconnected Do not connect, must be floated.
59 NC unconnected Do not connect, must be floated.
60 DB0M output Channel B differential LVDS output data D0 and D1 multiplexed, complement.
61 DB0P output Channel B differential LVDS output data D0 and D1 multiplexed, true.
62 DB2M output Channel B differential LVDS output data D2 and D3 multiplexed, complement.
63 DB2P output Channel B differential LVDS output data D2 and D3 multiplexed, true.
64 SDOUT output Serial interface register readout output when READOUT bit is enabled; high-impedance when READOUT = 0 and must float if unused.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Data Converters
Pins 65

CAD (KiCad official)

  • Symbol: ADS4242IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads4242irgcr-etched.step / ads4242irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4242irgcr.step / ads4242irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (96 pp, sha256 1d5b3fd659869db9, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF