component
VP3186SPG8
Public Made by Adomby adom
VIVA DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownVP3186SPG8
VIVA · DC-DC Converters · SOP-8-EP
VP3186SPG8 from VIVA, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Power ground for the converter power stage. |
| 2 | OC | input | Current limit setting: a resistor from OC to GND sets the peak switch current (2.1 A to 4.9 A over 20 kΩ to 43 kΩ), and leaving it floating selects the internal 5.5 A current limit. |
| 3 | IN | power_in | Supply input that must be driven from a 2.7 V to 5.5 V source to activate the converter, with a minimum 1 µF ceramic bypass capacitor placed near the pin. |
| 4 | EN | input | Chip enable: pulling EN above 1 V enables the converter and below 0.4 V shuts it off, and a 100 kΩ pull-up starts it automatically. |
| 5 | GND | power_in | Analog ground that must be connected to the exposed pad. |
| 6 | FB | input | Feedback input from an external resistor divider on the output, regulated to the internal reference, which the electrical characteristics give as 0.6 V (the pin table prints 1.26 V). |
| 7 | VSEN | input | Output sense input that connects to the DC output to improve conversion efficiency. |
| 8 | LX | output | Switch output connecting to the inductor and Schottky diode, rated -0.3 V to 18 V, with the trace to the input bypass capacitor kept short to reduce EMI. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VIVA |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VIN(IN, EN, FB) | -0.3 | 6 | V | 3 | ||
| Switch voltage range | VLX | -0.3 | 18 | V | 3 | ||
| Operating junction temperature range | TJ | -40 | 150 | oC | 3 | ||
| Storage temperature range | TSTG | -65 | 150 | oC | 3 | ||
| Electrostatic discharge, Human body model | 2 | kV | Human body model | 3 | |||
| Electrostatic discharge, Machine model | 200 | V | Machine model | 3 | |||
| Supply voltage | VIN(IN, EN, FB) | 2.7 | 5.5 | V | 3 | ||
| Operating free-air temperature range | TA | -40 | 85 | oC | 3 | ||
| Operating junction range | TJ | -40 | 125 | oC | 3 | ||
| Switch voltage range | VLX | 12 | V | Minimum printed as VIN+0.3 (not a numeric value) | 3 | ||
| Shutdown supply current | ISD | 1 | 3 | µA | VEN=0V | 4 | |
| Feedback voltage | VFB | 0.588 | 0.6 | 0.612 | V | VEN=2V | 4 |
| Current Limit Adjustable Range | IOC | 2.1 | 4.9 | A | IOC=20kΩ~43kΩ | 4 | |
| Quiescent current (VP3186A, no PSM version) | IQ | 0.4 | mA | VFB=0.7V, Non Switching | 4 | ||
| Quiescent current (VP3186B, PSM version) | IQ | 100 | µA | VFB=0.7V, Non Switching | 4 | ||
| Under voltage lockout | VUVLO | 2.4 | V | VIN Rising | 4 | ||
| UVLO Hystersis | VUVLOHYS | 200 | mV | 4 | |||
| Feedback bias current | IFB | 0.1 | µA | VFB=0.1V | 4 | ||
| Internal switch RDS(ON) | RDS(ON) | 100 | mΩ | ILX=1A | 4 | ||
| Current limit | 5.5 | A | VIN=3.2V, Duty Cycle=70% | 4 | |||
| Switch Leakage Current | ILX(LEAKAGE) | 2 | µA | VLX=12V, VEN=0V | 4 | ||
| Oscillation frequency | fOSC | 1 | MHz | 4 | |||
| Maximum duty cycle | DMAX | 90 | % | VFB=0V | 4 | ||
| Chip enable threshold | 1 | V | VEN rising | 4 | |||
| Chip shutdown threshold | 0.4 | V | VEN falling | 4 | |||
| Thermal shutdown threshold | 150 | oC | Design center value (*1) | 4 | |||
| Thermal resistance (Junction to Case) | θJC | 15 | oC/W | 3 | |||
| Thermal resistance (Junction to Air) | θJA | 75 | oC/W | 3 |
CAD (KiCad official)
- Symbol:
VP3186SPG8 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
vp3186spg8-etched.step/vp3186spg8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vp3186spg8.step/vp3186spg8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VIVA datasheet (11 pp, sha256
5aadba11ebfff565, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).