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NSD5604NE-DHTSTR

Public Made by Adom

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NOVOSENSE Gate Drivers, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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NSD5604NE-DHTSTR

NOVOSENSE · Gate Drivers · HTSSOP-20

NSD5604NE-DHTSTR from NOVOSENSE, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Integrated power switch ground, internally connected to the low side MOSFET sources; must be shorted externally to SGND.
2 GND power_in Integrated power switch ground, internally connected to the low side MOSFET sources; must be shorted externally to SGND.
3 Vz passive Load clamp voltage pin, must be shorted to pin 18 on the board and connected to the supply rail directly or through an external Zener/TVS diode (clamp voltage range 0 to 55 V).
4 IN1 input Channel 1 input, drive high to turn on low side OUT1; accepts PWM up to 200 kHz, with a typ 100 kΩ internal pulldown.
5 IN2 input Channel 2 input, drive high to turn on low side OUT2; accepts PWM up to 200 kHz, with a typ 100 kΩ internal pulldown.
6 IN3 input Channel 3 input, drive high to turn on low side OUT3; accepts PWM up to 200 kHz, with a typ 100 kΩ internal pulldown.
7 IN4 input Channel 4 input, drive high to turn on low side OUT4; accepts PWM up to 200 kHz, with a typ 100 kΩ internal pulldown.
8 SGND power_in Logic interface block signal ground, reference for logic; must be shorted externally to GND.
9 NC unconnected Not connected on NSD5604NE (this pin is the VDD5 LDO output only on NSD5604E).
10 nFAULT output Fault output, open drain, logic low when in fault condition (VM undervoltage, overcurrent, over temperature).
11 COD input Programmable cut-off delay during overcurrent; cannot be left floating: connect to SGND to disable cut-off, or a resistor (60 kΩ to 240 kΩ) to ground to set the delay RCOD/120 ms.
12 ILIM input Current limit adjustment; cannot be left floating: connect a resistor to ground to set the limit (60/RLIM(kΩ) A for 30 kΩ to 120 kΩ, 3 A typ below 20 kΩ).
13 VM power_in Supply voltage input, 8 V to 50 V operating (55 V absolute max), suggest >1 µF capacitor.
14 OUT4 output Power stage channel 4 low side output; can be paralleled with other channels for higher current.
15 OUT3 output Power stage channel 3 low side output; can be paralleled with other channels for higher current.
16 OUT2 output Power stage channel 2 low side output; can be paralleled with other channels for higher current.
17 OUT1 output Power stage channel 1 low side output; can be paralleled with other channels for higher current.
18 Vz passive Load clamp voltage pin, must be shorted to pin 3 on the board and connected to the supply rail directly or through an external Zener/TVS diode.
19 GND power_in Integrated power switch ground, internally connected to the low side MOSFET sources; must be shorted externally to SGND.
20 GND power_in Integrated power switch ground, internally connected to the low side MOSFET sources; must be shorted externally to SGND.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package HTSSOP-20
Category Motor Driver ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VM Power supply voltage (recommended) VM 8 50 V 5
Vz external clamp voltage (recommended) Vz 0 55 V 5
Logic input voltage (recommended) VINx 0 5 V 5
Logic input PWM frequency (recommended) fPWM 0 200 kHz 5
Power supply voltage (absolute max) VM -0.3 55 V 4
Vz voltage (absolute max) Vz -0.3 V Maximum printed as VDEMAG 4
Logic input/output voltage INx, nFault (absolute max) VINX, VnFAULT -0.3 6 V 4
Output voltage (absolute max) VOUTX -0.3 V Maximum printed as VDEMAG 4
COD, ILIM pin voltage (absolute max) VILIM, VCOD -0.3 6 V 4
Ambient operating temperature Ta -40 125 °C 5
Junction temperature Tj -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
VM operating voltage VM 8 50 V 5
VM undervoltage lockout, falling threshold VUVLO 6.5 7.5 V VM falls until UVLO triggers 5
VM undervoltage lockout, rising threshold VUVLO 7 8 V VM rises until operation recovers 5
Input logic low current IIL -5 5 μA VIN = 0 V 6
Input logic high current IIH 50 100 μA VIN = 5 V 6
OFF-state leakage ILEAK_OUTx -10 10 μA VOUT = 24V 6
Internal clamping voltage VDEMAG 53 58 65 V 6
Propagation delay INx to OUTx OFF->ON tPD 0.5 0.8 μs 6
Propagation delay INx to OUTx ON->OFF tPD 0.5 0.8 μs 6
Low-side FET on resistance at Ta=25 RDS(ON) 0.26 0.36 Ω VM = 24 V, I = 0.5 A, Ta=25 6
Catch diode forward voltage VFCD 1 1.2 V VM = 24 V, I = 0.5 A 6
ILIM current limitation threshold tolerance (RLIM<20kΩ, nominal 3 A) ILIM -30 30 % 0≤RLIM<20kΩ 7
ILIM current limitation threshold tolerance (30kΩ≤RLIM≤120kΩ, nominal 60/RLIM(kΩ) A) ILIM -30 30 % 30kΩ≤RLIM≤120kΩ 7
Cut off delay timing tolerance (nominal RCOD(kΩ)/120 ms) tCOD -30 30 % 60kΩ≤RCOD≤240kΩ 7
Chip central thermal shutdown temperature TSD_Central 150 160 180 °C 7
Channel thermal shutdown temperature TSD_Channel 150 160 180 °C 7
Thermal resistance, junction to case Rthjc 3 °C/W 5
Thermal resistance, junction to ambient, 2-layer PCB Rthja 50 °C/W on 2-layer PCB 5
Thermal resistance, junction to ambient, 4-layer PCB Rthja 39 °C/W on 4-layer PCB 5
VM operating supply current IVM 3 mA VM = 24V, VDD5 no load 5
VM undervoltage hysteresis VUVLO_HYS 500 mV 5
VM undervoltage deglitch time tUVLO 10 μs 5
Input logic low voltage VIL 0.8 V 6
Input logic high voltage VIH 2 V 6
Input logic hysteresis VHYS 0.5 V 6
Pulldown resistance to GND RPD 100 kΩ 6
Low-side FET on resistance at Ta=125 RDS(ON) 0.56 Ω VM = 24 V, I = 0.5 A, Ta=125 6
Output rise time tRISE 0.2 μs VM = 24 V, OUTx rising from 10% to 90%, Resistive load 6
Output fall time tFALL 0.2 μs VM = 24V, OUTx failing from 90% to 10%, Resistive load 6
Catch diode reverse current IRCD 10 μA Vrrm = 55 V 6
Thermal shutdown hysteresis THYS 20 °C 7
nFault output low voltage VOL 0.5 V Io = 2mA 7
Output high leakage current, nFault ILEAK_nFAULT 1 μA Vo = 5V 7

CAD (KiCad official)

  • Symbol: NSD5604NE-DHTSTR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: nsd5604ne-dhtstr-etched.step / nsd5604ne-dhtstr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsd5604ne-dhtstr.step / nsd5604ne-dhtstr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (15 pp, sha256 4a5c494393c2df93, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF