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SN74HC374N

Public Made by Adom

by adom

Texas Instruments Flip Flops, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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SN74HC374N

Texas Instruments · Flip Flops · DIP-20

SN74HC374N from Texas Instruments, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ~{OE} input Active-low output-enable input; when HIGH all eight Q outputs are placed in the high-impedance state, independent of clock or data; VIH min 3.15 V at VCC = 4.5 V.
2 1Q tri_state 3-state output of flip-flop 1; set to D1 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
3 1D input Data input of flip-flop 1; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
4 2D input Data input of flip-flop 2; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
5 2Q tri_state 3-state output of flip-flop 2; set to D2 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
6 3Q tri_state 3-state output of flip-flop 3; set to D3 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
7 3D input Data input of flip-flop 3; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
8 4D input Data input of flip-flop 4; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
9 4Q tri_state 3-state output of flip-flop 4; set to D4 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
10 GND power_in Ground reference, 0 V; continuous current through GND pin must not exceed ±70 mA.
11 CLK input Common rising-edge clock input for all eight flip-flops; minimum pulse width tw = 16 ns at VCC = 4.5 V; fclock max 30 MHz at VCC = 4.5 V.
12 5Q tri_state 3-state output of flip-flop 5; set to D5 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
13 5D input Data input of flip-flop 5; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
14 6D input Data input of flip-flop 6; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
15 6Q tri_state 3-state output of flip-flop 6; set to D6 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
16 7Q tri_state 3-state output of flip-flop 7; set to D7 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
17 7D input Data input of flip-flop 7; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
18 8D input Data input of flip-flop 8; logic level captured on positive transition of CLK; setup time tsu = 20 ns min at VCC = 4.5 V.
19 8Q tri_state 3-state output of flip-flop 8; set to D8 on rising CLK edge when OE is LOW; IOH = -6 mA, IOL = 6 mA at VCC = 4.5 V.
20 VCC power_in Positive supply voltage, 2 V to 6 V recommended; ICC max 80 µA quiescent at VCC = 6 V; decouple with 0.1 µF to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC374N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc374n-etched.step / sn74hc374n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc374n.step / sn74hc374n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 e72f5f2d1a24107d, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF