component

SI9407BDY-T1-E3

Public Made by Adom

by adom

Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorssi9407bdy-t1-e3factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SI9407BDY-T1-E3

Vishay Intertech · MOSFETs · SO-8

SI9407BDY-T1-E3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the P-channel MOSFET; the datasheet gives no pin-specific limit, so the device ratings VDS = -60 V and VGS = ±20 V apply.
2 S passive Source terminal of the P-channel MOSFET; the datasheet gives no pin-specific limit, so the device ratings VDS = -60 V and VGS = ±20 V apply.
3 S passive Source terminal of the P-channel MOSFET; the datasheet gives no pin-specific limit, so the device ratings VDS = -60 V and VGS = ±20 V apply.
4 G input Gate terminal of the P-channel MOSFET; gate-source voltage is rated at ±20 V.
5 D passive Drain terminal of the P-channel MOSFET; drain-source voltage is rated at -60 V.
6 D passive Drain terminal of the P-channel MOSFET; drain-source voltage is rated at -60 V.
7 D passive Drain terminal of the P-channel MOSFET; drain-source voltage is rated at -60 V.
8 D passive Drain terminal of the P-channel MOSFET; drain-source voltage is rated at -60 V.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS -60 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID -4.7 A TC = 25 °C (TJ = 150 °C) 1
Continuous drain current ID -3.8 A TC = 70 °C (TJ = 150 °C) 1
Continuous drain current ID -3.2 A TA = 25 °C, notes b, c 1
Continuous drain current ID -2.6 A TA = 70 °C, notes b, c 1
Pulsed drain current (10 μs width) IDM -20 A 10 μs width 1
Continuous source-drain diode current IS -4.2 A TC = 25 °C 1
Continuous source-drain diode current IS -2 A TA = 25 °C, notes b, c 1
Avalanche current IAS -15 A L = 0.1 mH 1
Single-pulse avalanche energy EAS 11 mJ 1
Maximum power dissipation PD 5 W TC = 25 °C 1
Maximum power dissipation PD 3.2 W TC = 70 °C 1
Maximum power dissipation PD 2.4 W TA = 25 °C, notes b, c 1
Maximum power dissipation PD 1.5 W TA = 70 °C, notes b, c 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Maximum junction-to-ambient RthJA 42 53 °C/W notes b, d 1
Maximum junction-to-foot (drain) RthJF 19 25 °C/W Steady state 1
Drain-source breakdown voltage VDS -60 V VGS = 0 V, ID = -250 μA 2
Gate-source threshold voltage VGS(th) -1 -3 V VDS = VGS, ID = -250 μA 2
Gate-source leakage IGSS -100 100 nA VDS = 0 V, VGS = ±20 V 2
Zero gate voltage drain current IDSS -1 μA VDS = -60 V, VGS = 0 V 2
Zero gate voltage drain current IDSS -10 μA VDS = -60 V, VGS = 0 V, TJ = 55 °C 2
On-state drain current ID(on) -20 A VDS -5 V, VGS = -10 V 2
Drain-source on-state resistance RDS(on) 0.1 0.12 Ω VGS = -10 V, ID = -3.2 A 2
Drain-source on-state resistance RDS(on) 0.126 0.15 Ω VGS = -4.5 V, ID = -2.9 A 2
Continuous source-drain diode current IS -4.2 A TC = 25 °C 2
Pulse diode forward current ISM -20 A 2
Body diode voltage VSD -0.8 -1.2 V IS = -2 A, VGS = 0 V 2
Body diode reverse recovery time trr 30 50 ns IF = -2 A, di/dt = -100 A/μs, TJ = 25 °C 2
Body diode reverse recovery charge Qrr 35 60 nC IF = -2 A, di/dt = -100 A/μs, TJ = 25 °C 2
Total gate charge Qg 14.5 22 nC VDS = -30 V, VGS = -10 V, ID = -3.2 A 2
Total gate charge Qg 8 12 nC VDS = -30 V, VGS = -4.5 V, ID = -3.9 A 2
Turn-on delay time td(on) 30 45 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise time tr 70 105 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -4.5 V, Rg = 1 Ω 2
Turn-off delay time td(off) 40 60 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -4.5 V, Rg = 1 Ω 2
Fall time tf 30 45 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -4.5 V, Rg = 1 Ω 2
Turn-on delay time td(on) 10 15 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -10 V, Rg = 1 Ω 2
Rise time tr 13 20 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 35 55 ns VDD = -30 V, RL = 11.5 Ω, ID -2.6 A, VGEN = -10 V, Rg = 1 Ω 2

CAD (KiCad official)

  • Symbol: SI9407BDY-T1-E3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si9407bdy-t1-e3-etched.step / si9407bdy-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si9407bdy-t1-e3.step / si9407bdy-t1-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 6c0cbf4304aecb8d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF