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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

BQ7694203PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7694203PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
2	VC9	input	Sense voltage input for the ninth cell from the bottom of the stack, balance current input for that cell, and return balance current for the tenth cell; maximum VSS+85 V.
3	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
4	VC8	input	Sense voltage input for the eighth cell from the bottom of the stack, balance current input for that cell, and return balance current for the ninth cell; maximum VSS+85 V.
5	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
6	VC7	input	Sense voltage input for the seventh cell from the bottom of the stack, balance current input for that cell, and return balance current for the eighth cell; maximum VSS+85 V.
7	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
8	VC6	input	Sense voltage input for the sixth cell from the bottom of the stack, balance current input for that cell, and return balance current for the seventh cell; maximum VSS+85 V.
9	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
10	VC5	input	Sense voltage input for the fifth cell from the bottom of the stack, balance current input for that cell, and return balance current for the sixth cell; maximum VSS+85 V.
11	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
12	VC4	input	Sense voltage input for the fourth cell from the bottom of the stack, balance current input for that cell, and return balance current for the fifth cell; maximum VSS+85 V.
13	VC3	input	Sense voltage input for the third cell from the bottom of the stack, balance current input for that cell, and return balance current for the fourth cell; maximum VSS+85 V.
14	VC2	input	Sense voltage input for the second cell from the bottom of the stack, balance current input for that cell, and return balance current for the third cell; maximum VSS+85 V.
15	VC1	input	Sense voltage input for the first cell from the bottom of the stack, balance current input for that cell, and return balance current for the second cell; maximum VSS+85 V.
16	VC0	input	Sense voltage input for the negative terminal of the first cell from the bottom of the stack and return balance current for that cell; connect through a resistor and capacitor to VSS (pin 17).
17	VSS	power_in	Device ground.
18	SRP	input	Analog input to the internal coulomb counter for the small voltage between SRP and SRN, where SRP is the top of the sense resistor; a charging current produces a positive voltage at SRP relative to SRN, and the coulomb counter range is ±200 mV.
19	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
20	SRN	input	Analog input to the internal coulomb counter for the small voltage between SRP and SRN, where SRN is the bottom of the sense resistor; if unused, connect to VSS (pin 17).
21	TS1	bidirectional	Thermistor input or general purpose ADC input (ADCIN range is limited to the REG18 pin voltage); open-drain output type.
22	TS2	bidirectional	Thermistor input that also functions as wakeup from SHUTDOWN, or general purpose ADC input; leave floating if the device is intended to enter SHUTDOWN mode.
23	TS3	bidirectional	Thermistor input or general purpose ADC input; if unused, can be left floating or connected to VSS.
24	REG18	power_out	Internal 1.8 V LDO output for internal use only (1.6 V to 2.0 V), requiring an external capacitor of 1.8 µF to 22 µF to VSS.
25	ALERT	bidirectional	Multifunction pin configurable as ALERT output, HDQ I/O, thermistor input, general purpose ADC input, or general purpose digital output; open-drain when configured as HDQ.
26	SCL	bidirectional	Multifunction open-drain pin configurable as I2C SCL or SPI_SCLK.
27	SDA	bidirectional	Multifunction open-drain pin configurable as I2C SDA or SPI_MISO.
28	HDQ	bidirectional	Multifunction pin configurable as HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output.
29	CFETOFF	bidirectional	Multifunction pin configurable as CFETOFF input (driven low to disable the CHG and PCHG FETs), SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output.
30	DFETOFF	bidirectional	Multifunction pin configurable as DFETOFF or BOTHOFF input (asserted to disable the DSG and PDSG FETs, or all four FETs for BOTHOFF), thermistor input, general purpose ADC input, or general purpose digital output.
31	DCHG	bidirectional	Multifunction pin configurable as DCHG fault output (signals a fault that would disable the CHG driver), thermistor input, general purpose ADC input, or general purpose digital output.
32	DDSG	bidirectional	Multifunction pin configurable as DDSG fault output (signals a fault that would disable the DSG driver), thermistor input, general purpose ADC input, or general purpose digital output.
33	RST_SHUT	input	Digital input to reset the device; if held high for 1 second the device enters SHUTDOWN mode, and it should be driven low during normal operation (connect to VSS if unused).
34	REG2	power_out	Second LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V; may be left floating or connected to VSS if unused.
35	REG1	power_out	First LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V, specified for 0 mA to 45 mA load; requires a 1 µF capacitor to VSS.
36	REGIN	input	Input pin for the REG1 and REG2 LDOs; connect to VSS if unused.
37	BREG	output	Base control signal for the external pre-regulator transistor; connect to REGIN if REGIN is driven externally and BREG is unused, otherwise to VSS if both are unused.
38	FUSE	bidirectional	Fuse sense and drive pin that drives the gate of an NFET to blow a chemical fuse on a permanent fail, and is high-impedance when not asserted; may be left floating or connected to VSS if unused.
39	PDSG	output	Predischarge PFET control output; leave floating if not used.
40	PCHG	output	Precharge PFET control output; leave floating if not used.
41	LD	bidirectional	Load detect pin with an internal pullup current of 35 µA to 172 µA from BAT when VLD is at VSS; if the DSG driver is unused, connect through a series resistor to PACK+ or to VSS.
42	PACK	input	Pack sense input pin; maximum VSS+85 V.
43	DSG	output	NMOS discharge FET drive output; leave floating if not used.
44	NC	unconnected	This pin is not connected to silicon and may be left floating, connected to an adjacent pin, or connected to VSS.
45	CHG	output	NMOS charge FET drive output; leave floating if not used.
46	CP1	bidirectional	Charge pump capacitor pin; if the charge pump is unused, connect to BAT (pin 47), which adds about 200 µA of supply current when the charge pump is enabled.
47	BAT	power_in	Primary power supply input; recommended operating range 4.7 V to 55 V, absolute maximum VSS+85 V.
48	VC10	input	Sense voltage input for the tenth cell from the bottom of the stack, balance current input for that cell, and top-of-stack measurement point; maximum VSS+85 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	Power Management (PMIC)
Pins	48

CAD (KiCad official)

Symbol: BQ7694203PFBR
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: bq7694203pfbr-etched.step / bq7694203pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7694203pfbr.step / bq7694203pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (85 pp, sha256 a976a88e92abb957, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF