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NCV57200DR2G

Public Made by Adom

by adom

onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

NCV57200DR2G

onsemi · Gate Drivers · SOIC-8

NCV57200DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Low-side and main power supply, recommended up to 20 V, with the UVLO enabling operation above a typical VUVLO1-OUT-ON and a bypass capacitor to GND required close to the pin.
2 HIN input High-side non-inverting gate driver input with a 125 kΩ pull-down, 3.3 V logic thresholds up to VDD, and a minimum pulse width required before HO reacts.
3 LIN input Low-side non-inverting gate driver input with a 125 kΩ pull-down, 3.3 V logic thresholds up to VDD, and a minimum pulse width required before LO reacts.
4 GND power_in Logic ground and low-side driver return.
5 LO output Low-side driver output to the IGBT gate, actively pulled low during startup and UVLO1 condition, with deadtime and interlock preventing cross conduction with HO.
6 VS power_in Bootstrap return or high-side floating supply offset, with the recommended operating range of −800 V to +800 V.
7 HO output Galvanically isolated high-side driver output to the IGBT gate, actively pulled low during startup and UVLO2 condition, with deadtime and interlock preventing cross conduction with LO.
8 VB power_in Bootstrap or high-side floating power supply, recommended up to VS+20 V, requiring a good quality bypass capacitor from VB to VS placed close to the pins.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-Side Offset Voltage VS -900 900 V 5
High-Side Offset Voltage (tp < 500 ns) -900 900 V tp < 500 ns 5
High-Side Supply Voltage VB -900 900 V 5
High-Side Supply Voltage (tp < 500 ns) -900 900 V tp < 500 ns 5
Low-Side and Logic-Fixed Supply Voltage VDD -0.3 25 V 5
High-Side Floating Supply Voltage VBS -0.3 25 V 5
Allowable Offset Voltage Slew Rate dVS/dt -50 50 V/ns 5
Maximum Junction Temperature TJ(max) -40 150 °C 5
Storage Temperature Range TSTG -65 150 °C 5
ESD Capability, Human Body Model ESDHBM -4 4 kV 5
ESD Capability, Charged Device Model ESDCDM -2 2 kV 5
High-Side Supply Offset Voltage VS -800 800 V 5
Low-Side Supply Voltage VDD 20 V 5
Ambient Temperature TA -40 125 °C 5
VBS Supply Under Voltage Output Enabled VUVLO2−OUT−ON 11 11.5 12 V 6
VBS Supply Under Voltage Output Disabled VUVLO2−OUT−OFF 10 10.5 11 V 6
VDD Supply Under Voltage Output Enabled VUVLO1−OUT−ON 12 12.5 13 V 6
VDD Supply Under Voltage Output Disabled VUVLO1−OUT−OFF 11 11.5 12 V 6
Leakage Current Between VS and GND IHV_LEAK1 20 200 nA VS = ± 800 V, TA = 25°C 6
Leakage Current Between VS and GND IHV_LEAK2 600 nA VS = ± 800 V, TA = −40°C to 125°C 6
Quiescent Current VBS Supply (VB Only) IQBS1 260 325 A HO = Low 6
Quiescent Current VBS Supply (VB Only) IQBS2 330 440 A HO = High 6
Quiescent Current VDD Supply (VDD Only) IQDD1 380 440 A VLIN = Float, VHIN = 0 V 6
Quiescent Current VDD Supply (VDD Only) IQDD2 440 500 A VLIN = 3.3 V, VHIN = 0 V 6
Quiescent Current VDD Supply (VDD Only) IQDD3 2.4 3 mA VLIN = 0 V, VHIN = 3.3 V 6
Low Level Input Voltage VIL 0.9 V 6
High Level Input Voltage VIH 2.4 V 6
Logic “1” Input Bias Current ILIN1+, IHIN1+ 25 50 A VLIN = 3.3 V, VHIN = 3.3 V 6
Logic “1” Input Bias Current ILIN2+, IHIN2+ 100 150 A VLIN = 20 V, VHIN = 20 V, VDD = VBS = 20 V 6
Logic “0” Input Bias Current ILIN−, IHIN− 40 100 nA VLIN = 0 V, VHIN = 0 V 6
Output Low State VOL1 0.2 0.3 V ISINK = 200 mA, TA = 25°C 6
Output Low State VOL2 0.5 V ISINK = 200 mA, TA = −40°C to 125°C 6
Output High State VOH1 14.4 14.5 V ISRC = 200 mA, TA = 25°C 6
Output High State VOH2 14 V ISRC = 200 mA, TA = −40°C to 125°C 6
Clamping Voltage (VHO, VB) / (VLO, VDD) VCLAMP−OUT 0.8 1.3 V IHO = 100 mA, ILO = 100 mA (pulse test, tCLPmax = 10 s) 7
HO High Propagation Delay tPD−ON−H 60 90 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 7
HO Low Propagation Delay tPD−OFF−H 60 90 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 7
Propagation Delay Distortion(HS) (= tPD−ON − tPD−OFF) tDISTORT−H -25 0 25 ns PW >150 ns 7
LO High Propagation Delay tPD−ON−L 60 90 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 7
LO Low Propagation Delay tPD−OFF−L 60 90 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 7
Propagation Delay Distortion(LS) (= tPD−ON − tPD−OFF) tDISTORT−L -25 0 25 ns PW >150 ns 7
High Prop Delay Distortion between High and Low Sides tDISTORT−HLH -25 0 25 ns PW > 150 ns 7
Low Prop Delay Distortion between High and Low Sides tDISTORT−HLL -25 0 25 ns PW > 150 ns 7
Rise Time(HS) tRISE−H 13 ns CLOAD = 1 nF, 10% to 90% of Output Change 7
Fall Time(HS) tFALL−H 8 ns CLOAD = 1 nF, 90% to 10% of Output Change 7
Rise Time(LS) tRISE−L 13 ns CLOAD = 1 nF, 10% to 90% of Output Change 7
Fall Time(LS) tFALL−L 8 ns CLOAD = 1 nF, 90% to 10% of Output Change 7
Deadtime Matching tMDT 10 ns 7
Minimum Pulse Width Filtering Time tMIN1, tMIN2 10 40 ns TA = 25°C 7
VDD Supply Voltage Output Enabled/Disabled Hysteresis VUVLO1−HYST 1 V 6
VBS Supply Voltage Output Enabled/Disabled Hysteresis VUVLO2−HYST 1 V 6
Peak Driver Current, Sink IPK−SNK1 2.3 A VHO = VLO = 15 V 6
Peak Driver Current, Sink IPK−SNK2 2.1 A VHO = VLO = 9 V (near Miller Plateau) 6
Peak Driver Current, Source IPK−SRC1 1.9 A VHO = VLO = 0 V 6
Peak Driver Current, Source IPK−SRC2 1.5 A VHO = VLO = 9 V (near Miller Plateau) 6
UVLO Fall Delay (HO and LO) tUV1 1300 ns 7
UVLO Rise Delay (HO and LO) tUV2 1100 ns 7
Deadtime, HO Delays tDT1 340 ns VLIN/HIN = 0 V and 3.3 V 7
Deadtime, LO Delays tDT2 350 ns VLIN/HIN = 0 V and 3.3 V 7
Thermal Resistance, Junction−to−Air RJA 167 °C/W 5

CAD (KiCad official)

  • Symbol: NCV57200DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv57200dr2g-etched.step / ncv57200dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv57200dr2g.step / ncv57200dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 422fc58fffa1d1e1, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF