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LP87702DRHBRQ1
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLP87702DRHBRQ1
Texas Instruments · Power Management - Specialized · VQFN-32-EP(5x5)
LP87702DRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nINT | output | Open-drain interrupt output, active LOW, pulled low when a flag bit is set and released high after all flags and pending interrupts are cleared. |
| 2 | FB_B0 | passive | Output voltage feedback input for Buck0 (remote sensing to compensate IR drop at the point of load). |
| 3 | FB_B1 | passive | Output voltage feedback input for Buck1 (remote sensing to compensate IR drop at the point of load). |
| 4 | AGND | power_in | Analog ground pin of the device. |
| 5 | VANA | power_in | Supply voltage for analog and digital blocks, rated 2.8 V to 5.5 V; must be connected to the same node as VIN_Bx. |
| 6 | WD_RESET | output | Reset output from the window watchdog; it is active for 10 ms or 7.5 ms plus 10 ms or 15 ms depending on watchdog settings. |
| 7 | WDI | input | Digital input signal for the window watchdog; logic input rated 0 V to VANA. |
| 8 | VOUT_BST | power_out | Boost converter output (5-V boost); bypass switch output when bypass mode is selected. |
| 9 | SW_BST | power_in | Boost input; bypass switch input when bypass mode is selected, rated 2.8 V to 5.5 V. |
| 10 | PGND_BST | power_in | Power ground for the boost converter. |
| 11 | NRST | input | Reset signal input for the device; driving it low disables all converters and resets registers to default values. |
| 12 | GPO0 | output | General purpose digital output 0, configurable as push-pull (VANA level) or open-drain. |
| 13 | VIN_B1 | power_in | Input for Buck1; VIN_Bx pins must be connected together in the application and locally bypassed, rated 2.8 V to 5.5 V. |
| 14 | VIN_B1 | power_in | Input for Buck1; VIN_Bx pins must be connected together in the application and locally bypassed, rated 2.8 V to 5.5 V. |
| 15 | SW_B1 | power_out | Buck1 switch node. |
| 16 | SW_B1 | power_out | Buck1 switch node. |
| 17 | PGND_B1 | power_in | Power ground for Buck1. |
| 18 | PGND_B1 | power_in | Power ground for Buck1. |
| 19 | EN1 | input | Programmable Enable 1 signal used for start-up and shutdown sequencing. |
| 20 | SCL | input | Serial interface clock input for I2C access; connect a pullup resistor. Alternative function is programmable to the enable 2 signal. |
| 21 | SDA | bidirectional | Serial interface data input and output for I2C access; connect a pullup resistor. Alternative function is programmable to the enable 3 signal. |
| 22 | CLKIN | bidirectional | External clock input to synchronize switching; alternative functions are general purpose digital output 2 (GPO2) and watchdog disable (WD_DIS). |
| 23 | PGND_B0 | power_in | Power ground for Buck0. |
| 24 | PGND_B0 | power_in | Power ground for Buck0. |
| 25 | SW_B0 | power_out | Buck0 switch node. |
| 26 | SW_B0 | power_out | Buck0 switch node. |
| 27 | VIN_B0 | power_in | Input for Buck0; VIN_Bx pins must be connected together in the application and locally bypassed, rated 2.8 V to 5.5 V. |
| 28 | VIN_B0 | power_in | Input for Buck0; VIN_Bx pins must be connected together in the application and locally bypassed, rated 2.8 V to 5.5 V. |
| 29 | PG0 | output | Programmable power-good indication output for Buck0 and related monitoring. |
| 30 | VMON1 | input | Voltage monitoring input 1, rated 0 V to 5.5 V. |
| 31 | VMON2 | input | Voltage monitoring input 2, rated 0 V to 5.5 V. |
| 32 | PG1 | output | Programmable power-good indication output; alternative function is general purpose digital output 1 (GPO1). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on input power connections (VIN_B0, VIN_B1, SW_BST, VANA) | -0.3 | 6 | V | 6 | |||
| Voltage on boost output (VOUT_BST) | -0.3 | 6 | V | 6 | |||
| Voltage on logic pins (NRST, EN1, nINT) | -0.3 | 6 | V | Input or output pins | 6 | ||
| Junction temperature | TJ-MAX | -40 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Maximum lead temperature | 260 | °C | Soldering, 10 sec. | 6 | |||
| Voltage on buck switch nodes (SW_B0, SW_B1) | -0.3 | V | Max (VIN_Bx + 0.3 V) with 6-V maximum | 6 | |||
| Voltage on buck voltage sense nodes (FB_B0, FB_B1) | -0.3 | V | Max (VANA + 0.3 V) with 6-V maximum | 6 | |||
| Voltage on voltage monitoring pins (SCL, SDA, VMON1, VMON2) | -0.3 | V | Max (VANA + 0.3 V) with 6-V maximum | 6 | |||
| Voltage on logic pins (PG0, PG1, GPO0, CLKIN, WDI, WD_RESET) | -0.3 | V | Max (VANA + 0.3 V) with 6-V maximum | 6 | |||
| Voltage on input power connections | 2.8 | 5.5 | V | VIN_B0, VIN_B1, SW_BST, VANA | 6 | ||
| Voltage on voltage monitoring pins | 0 | 5.5 | V | VMON1, VMON2 | 6 | ||
| Voltage on logic pins (input or output pins) | 0 | 5.5 | V | NRST, EN1, EN2, EN3, nINT | 6 | ||
| Voltage on logic pins (input or output pins) | 0 | V | PG0, PG1 (GPO1), GPO0, CLKIN (GPO2), WDI, WD_RESET; max VANA | 6 | |||
| Voltage on I2C interface | 0 | 1.95 | V | SCL, SDA, High-Speed mode | 6 | ||
| Voltage on I2C interface | 0 | 3.6 | V | SCL, SDA, Standard, Fast, Fast+ modes; max VANA with 3.6-V maximum | 6 | ||
| Junction temperature | TJ | -40 | 140 | °C | 6 | ||
| Ambient temperature | TA | -40 | 125 | °C | 7 | ||
| Input filtering capacitance for buck converters | CIN_BUCK | 1.9 | 10 | µF | Effective capacitance, from VIN_Bx to PGND_Bx | 7 | |
| Output filtering capacitance for buck converters | COUT_BUCK | 15 | 22 | 100 | µF | Effective total capacitance; maximum includes POL capacitance | 7 |
| Output filtering capacitance for boost converter | COUT_BST | 10 | 22 | 40 | µF | Effective capacitance | 7 |
| Input and output capacitor ESR | ESRC | 2 | 10 | mΩ | [1-10] MHz | 7 | |
| Inductor for buck converters tolerance | LBUCK | -30 | 30 | % | Inductance of the inductor | 7 | |
| Inductor for boost converters tolerance | LBST | -30 | 30 | % | Inductance of the inductor | 7 | |
| Input voltage range | V(VIN_Bx), V(VANA) | 2.8 | 3.3 | 5.5 | V | 7 | |
| Output voltage programmable voltage range | VOUT_Bx | 0.7 | 1 | 3.36 | V | Programmable voltage range | 7 |
| Output current | IOUT_Bx | 3.5 | A | Output current | 7 | ||
| Minimum voltage difference between V(VIN_Bx) and VOUT_Bx | V(VIN_Bx), VOUT | 0.8 | V | IOUT_Bx ≤ 2 A | 8 | ||
| Minimum voltage difference between V(VIN_Bx) and VOUT_Bx | V(VIN_Bx), VOUT | 1 | V | IOUT_Bx > 2 A | 8 | ||
| DC output voltage accuracy | -20 | 20 | mV | Force PWM mode, VOUT < 1.0 V | 8 | ||
| DC output voltage accuracy | -2 | 2 | % | Force PWM mode, VOUT ≥ 1.0 V | 8 | ||
| DC output voltage accuracy | -20 | 40 | mV | PFM mode, VOUT < 1.0 V, average output voltage level is increased by max. 20 mV | 8 | ||
| Ripple voltage PWM mode | 5 | mVp-p | PWM mode, VOUT = 1.2 V, fSW = 4 MHz, COUT = 22 + 22 µF | 8 | |||
| Ripple voltage PFM mode | 25 | mVp-p | PFM mode, L = 0.47 µH, COUT = 22 + 22 µF | 8 | |||
| DC line regulation | DCLNR | -0.05 | 0.05 | %/V | IOUT = IOUT(max) | 8 | |
| Transient load step response | TLDSR | -65 | 65 | mV | IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM mode, VVIN_Bx = 3.3V, VOUT_Bx = 1.2 V, COUT = 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz | 8 | |
| Transient line response | TLNSR | -20 | 20 | mV | V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) | 8 | |
| Forward current limit for both bucks (peak for every switching cycle) | ILIM FWD | 1.5 | 4.5 | A | Programmable range | 8 | |
| Forward current limit accuracy | ILIM FWD | -5 | 7.5 | 20 | % | V(VIN_Bx) ≥ 3 V, ILIM = 4 A | 8 |
| Negative current limit | ILIM NEG | 1.6 | 2 | 3 | A | 8 | |
| On-resistance, high-side FET (buck) | RDS(ON) BUCK HS FET | 60 | 110 | mΩ | Each phase, between VIN_Bx and SW_Bx pins (I = 1.0 A) | 8 | |
| On-resistance, low-side FET (buck) | RDS(ON) BUCK LS FET | 55 | 80 | mΩ | Each phase, between SW_Bx and PGND_Bx pins (I = 1.0 A) | 8 | |
| Switching frequency, PWM mode | ƒSW | 1.8 | 2 | 2.2 | MHz | 2-MHz setting or VOUT_Bx < 0.8 V | 8 |
| Switching frequency, PWM mode | ƒSW | 2.7 | 3 | 3.3 | MHz | 3-MHz setting and VOUT_Bx ≥ 0.8 V | 8 |
| Switching frequency, PWM mode | ƒSW | 3.6 | 4 | 4.4 | MHz | 4-MHz setting and VOUT_Bx ≥ 1.1 V | 8 |
| Output voltage slew rate | -15 | 10 | 15 | mV/µs | SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V | 8 | |
| Output pull-down resistance | 75 | 125 | 175 | Ω | Converter disabled | 9 | |
| Input voltage range for boost power inputs | VIN_BST | 2.8 | 3.3 | 4 | V | 9 | |
| Input voltage range when bypass switch mode selected | 4.5 | 5.5 | V | Bypass switch mode | 9 | ||
| DC output voltage accuracy, boost mode | VOUT_BST_DC | -3 | 3 | % | Default output voltage | 9 | |
| Output current | IOUT_BST | 0.6 | A | Both boost and bypass mode | 9 | ||
| Transient load step response, boost mode | TLDSR | -220 | 220 | mV | IOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22 µF effective output capacitance, VIN > 3 V | 9 | |
| On-resistance, high-side FET (boost) | RDS(ON) BST HS FET | 145 | 220 | mΩ | Pin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA) | 9 | |
| On-resistance, low-side FET (boost) | RDS(ON) BST LS FET | 90 | 175 | mΩ | Pin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA) | 9 | |
| Junction-to-ambient thermal resistance | RθJA | 31.7 | °C/W | RHB (VQFN) 32 pins | 7 | ||
| Junction-to-case (bottom) thermal resistance | RθJCbot | 1.1 | °C/W | RHB (VQFN) 32 pins | 7 |
CAD (KiCad official)
- Symbol:
LP87702DRHBRQ1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
lp87702drhbrq1-etched.step/lp87702drhbrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp87702drhbrq1.step/lp87702drhbrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (102 pp, sha256
25ba447ead3e65de, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).