component
LMR16010PDDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLMR16010PDDAR
Texas Instruments · DC-DC Converters · SO-8
LMR16010PDDAR from Texas Instruments, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1 µF capacitor from BOOT to SW. Absolute max BOOT-to-SW = 6.5 V; BOOT-to-GND up to 71 V. |
| 2 | VIN | power_in | Input supply pin, 4.3 V to 60 V operating range (65 V absolute max). Connect to power supply and bypass capacitor CIN; keep CIN return to GND short. |
| 3 | EN | input | Precision enable input with internal pull-up current source. Pull below 1.2 V (typ) to disable; float or tie to VIN to enable. Can be used with a two-resistor divider to program input UVLO. Threshold typ 1.20 V, absolute max 65 V. |
| 4 | RT/SYNC | bidirectional | Resistor timing or external clock input. Tie a resistor to GND to program switching frequency (200 kHz-2.5 MHz). Driving above the PLL upper threshold turns the pin into a high-impedance sync clock input (250 kHz-2.3 MHz). Absolute max 3.6 V. |
| 5 | FB | input | Feedback input pin. Connect to the external resistor divider from VOUT to set the output voltage; internal reference VFB = 0.750 V. Do not short to ground during operation. Absolute max 7 V. |
| 6 | PGOOD | output | Power-Good open-drain output flag. Requires a 10 kΩ to 100 kΩ pull-up to a logic rail or DC voltage no higher than 7 V. Asserts when FB is within ~94%/107% of reference. |
| 7 | GND | power_in | System ground pin. Return for input bypass and internal analog/power ground. |
| 8 | SW | power_out | Switching output of the regulator, internally connected to the high-side power MOSFET (155 mΩ typ). Connect to the power inductor; also serves as the low-side reference for the BOOT capacitor. Operating range -1 V to 60 V (absolute max -3 V to 65 V). |
| 9 | Thermal Pad | power_in | Exposed PowerPAD on the underside of the HSOIC package - the major heat dissipation path of the die. Must be soldered to the PCB ground plane for thermal performance and electrically tied to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
LMR16010PDDAR
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Buck regulator input voltage (VIN pin) | VIN | 4.3 | 60 | V | 4 | ||
| Buck regulator output voltage | VOUT | 0.8 | 50 | V | 4 | ||
| BOOT pin voltage | BOOT | 66 | V | 4 | |||
| SW pin voltage | SW | -1 | 60 | V | 4 | ||
| FB pin voltage | FB | 0 | 5 | V | 4 | ||
| EN pin voltage | EN | 0 | 60 | V | 4 | ||
| RT/SYNC pin voltage | RT/SYNC | 0 | 3.3 | V | 4 | ||
| PGOOD to GND voltage | PGOOD | 0 | 5 | V | 4 | ||
| Switching frequency range at RT mode | fSW | 200 | 2500 | kHz | 4 | ||
| Switching frequency range at SYNC mode | fSW | 250 | 2300 | kHz | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VIN, EN to GND | VIN, EN | -0.3 | 65 | V | 4 | ||
| BOOT to GND | BOOT | -0.3 | 71 | V | 4 | ||
| FB to GND | FB | -0.3 | 7 | V | 4 | ||
| RT/SYNC to GND | RT/SYNC | -0.3 | 3.6 | V | 4 | ||
| PGOOD to GND | PGOOD | -0.3 | 7 | V | 4 | ||
| BOOT to SW | BOOT-SW | 6.5 | V | 4 | |||
| SW to GND | SW | -3 | 65 | V | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| VIN operation input voltage | VIN | 4.3 | 60 | V | 5 | ||
| UVLO rising threshold | UVLO | 3.8 | 4 | 4.2 | V | Rising threshold | 5 |
| Shutdown supply current | ISHDN | 1 | 3 | μA | VEN = 0 V, TA = 25 °C, 4.3 V ≤ VIN ≤ 60 V | 5 | |
| PGOOD leakage current at high level output | IPG | 10 | 200 | nA | VPull-Up = 5 V | 5 | |
| Minimum VIN for valid PGOOD output | VIN_PG_MIN | 1.6 | 1.95 | V | VPull-Up < 5 V at IPull-Up = 100 μA | 5 | |
| EN threshold voltage | VEN_TH | 1.05 | 1.2 | 1.38 | V | 5 | |
| Feedback voltage | VFB | 0.746 | 0.75 | 0.754 | V | TJ = 25 °C | 5 |
| Feedback voltage | VFB | 0.735 | 0.75 | 0.765 | V | TJ = -40 °C to 125 °C | 5 |
| High-side MOSFET on-resistance | RDS_ON | 155 | 320 | mΩ | VIN = 12 V, BOOT to SW = 5.8 V | 6 | |
| High-side MOSFET current limit | ILIMT | 1.45 | 1.75 | 2.1 | A | VIN = 12 V, TA = 25 °C, Open Loop | 6 |
| Switching frequency | fSW | 1758 | 1912 | 2066 | kHz | RT = 11.5 kΩ | 7 |
| Switching frequency range at SYNC mode | fSW | 250 | 2300 | kHz | 7 | ||
| SYNC clock high level threshold | VSYNC_HI | 1.7 | V | 7 | |||
| SYNC clock low level threshold | VSYNC_LO | 0.5 | V | 7 | |||
| Minimum SYNC input pulse width | TSYNC_MIN | 30 | ns | Measured at 500 kHz, VSYNC_HI > 3 V, VSYNC_LO < 0.3 V | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 42.5 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 9.9 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 25.4 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 56.1 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.8 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 25.5 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
LMR16010PDDAR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
lmr16010pddar-etched.step/lmr16010pddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr16010pddar.step/lmr16010pddar.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
lmr16010pddar.step |
123 KB | You want the bare part, or you mark your own boards. |
lmr16010pddar-etched.step |
2.4 MB | You want the part with LMR16010PDDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 615 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
d8c3ccade909e351, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).