component
2SK208-R
Public Made by Adomby adom
TOSHIBA JFETs, TO-236-3(SOT-23-3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown2SK208-R
TOSHIBA · JFETs · TO-236-3(SOT-23-3)
2SK208-R from TOSHIBA, in a TO-236-3(SOT-23-3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SOURCE | passive | Source terminal of the N-channel junction FET. |
| 2 | DRAIN | passive | Drain terminal of the N-channel junction FET; IDSS is 0.3 to 6.5 mA at VDS = 10 V, VGS = 0. |
| 3 | GATE | passive | Gate terminal; gate-drain voltage VGDS is -50 V, gate current IG max 10 mA, and IGSS is -1.0 nA max at VGS = -30 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TO-236-3(SOT-23-3) |
| Category | Triode/MOS Tube/Transistor |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-drain voltage | VGDS | -50 | V | Ta = 25°C | 1 | ||
| Gate current | IG | 10 | mA | Ta = 25°C | 1 | ||
| Drain power dissipation | PD | 100 | mW | Ta = 25°C | 1 | ||
| Junction temperature | Tj | 125 | °C | Ta = 25°C | 1 | ||
| Storage temperature range | Tstg | -55 | 125 | °C | Ta = 25°C | 1 | |
| Gate cut-off current | IGSS | -1 | nA | VGS = −30 V, VDS = 0 | 1 | ||
| Gate-drain breakdown voltage | V(BR)GDS | -50 | V | VDS = 0, IG = −100 μA | 1 | ||
| Drain current (R grade) | IDSS | 0.3 | 0.75 | mA | VDS = 10 V, VGS = 0; IDSS classification R | 1 | |
| Drain current (all grades) | IDSS | 0.3 | 6.5 | mA | VDS = 10 V, VGS = 0 | 1 | |
| Gate-source cut-off voltage | VGS(OFF) | -0.4 | -5 | V | VDS = 10 V, ID = 0.1 μA | 1 | |
| Forward transfer admittance | /Yfs/ | 1.2 | mS | VDS = 10 V, VGS = 0, f = 1 kHz | 1 | ||
| Input capacitance | Ciss | 8.2 | pF | VDS = 10 V, VGS = 0, f = 1 MHz | 1 | ||
| Reverse transfer capacitance | Crss | 2.6 | pF | VGD = −10 V, ID = 0, f = 1 MHz | 1 | ||
| Noise figure | NF | 0.5 | dB | VDS = 15 V, VGS = 0, RG = 100 kΩ, f = 120 Hz | 1 |
CAD (KiCad official)
- Symbol:
2SK208-R - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: TO-236-3(SOT-23-3) (KiCad packages3D, STEP)
- 3D model files:
2sk208-r-etched.step/2sk208-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2sk208-r.step/2sk208-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (4 pp, sha256
84a99e5e3a8b07e4, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).