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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS7A8300ARGWT

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(5x5)

TPS7A8300ARGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT	output	Regulated output pin that requires a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) to ground for stability, placed as close as possible to the output.
2	SNS	input	Output voltage sense input that connects to the load side of the output trace only when the ANY-OUT feature is used, and must otherwise be left floating.
3	FB	input	Feedback pin to the error amplifier; a 10-nF feed-forward capacitor from FB to OUT is optional but may disrupt power-good (PG) functionality.
4	PG	output	Active-high open-drain power-good output that indicates when the output voltage reaches VIT(PG) of the target, with a 10 kΩ to 100 kΩ pullup resistor recommended.
5	50mV	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
6	100mV	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
7	200mV	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
8	GND	power_in	Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection.
9	400mV	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
10	800mV	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
11	1.6V	input	TPS7A8300A ANY-OUT voltage setting pin tied to an internal feedback network; connect to GND to raise the output voltage, to SNS to increase resolution at the cost of range, or leave floating when not in use.
12	BIAS	input	BIAS supply input (3.0 V to 6.5 V) that enables low-input, low-output operation and improves DC and AC performance for VIN ≤ 2.2 V, requiring a 1-µF (0.47-µF minimum) capacitor to ground, or floating/grounding when unused.
13	NR/SS	passive	Noise-reduction and soft-start pin; a 10-nF or larger capacitor from NR/SS to GND, placed as close as possible to the pin, maximizes AC performance.
14	EN	input	Enable pin where logic high enables the device and logic low disables it, with the pin tied to IN or BIAS if enable functionality is not required; enable voltage range is 0 V to VIN.
15	IN	power_in	Input supply pin (1.1 V to 6.5 V) that requires a 10-µF or larger ceramic capacitor (5 µF minimum) from IN to ground placed as close as possible to the input.
16	IN	power_in	Input supply pin (1.1 V to 6.5 V) that requires a 10-µF or larger ceramic capacitor (5 µF minimum) from IN to ground placed as close as possible to the input.
17	IN	power_in	Input supply pin (1.1 V to 6.5 V) that requires a 10-µF or larger ceramic capacitor (5 µF minimum) from IN to ground placed as close as possible to the input.
18	GND	power_in	Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection.
19	OUT	output	Regulated output pin that requires a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) to ground for stability, placed as close as possible to the output.
20	OUT	output	Regulated output pin that requires a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) to ground for stability, placed as close as possible to the output.
21	Thermal Pad	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-20-EP(5x5)
Category	Power Management (PMIC)
Pins	21

CAD (KiCad official)

Symbol: TPS7A8300ARGWT
Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
3D model files: tps7a8300argwt-etched.step / tps7a8300argwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a8300argwt.step / tps7a8300argwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (63 pp, sha256 4b23b1f5239092dc, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF